Synthesis of low power folded programmable coefficient FIR digital filters (short paper)

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Synthesis of low power folded programmable coefficient FIR digital filters (short paper)

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 153 - 156

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Vijay Sundararajan	Dept. of ECE, University of Minnesota, Minneapolis, MN
Keshab K. Parhi	Dept. of ECE, University of Minnesota, Minneapolis, MN

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 1

Additional Information:

references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K. K. Parhi, C. Y. Wang, and A. P. Brown, "Synthesis of Control Circuits in Folded Pipelined DSP architectures," IEEE Journal of Solid State Circuits, vol. 27, no. 1, pp. 29-43, 1992.
	2	Tracy C. Denk , Keshab K. Parhi, Synthesis of folded pipelined architectures for multirate DSP algorithms, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.4, p.595-607, Dec. 1998 [doi>10.1109/92.736133]
	3	V. Sundararajan and K. K. Parhi, "Synthesis of Folded Multidimensional DSP Systems," in Proceedings of ISCAS-98, (Monterey, CA, USA), June 1998.
	4	G. Goossens, J. Rabaey, J. Vandwalle, and H. De Man, "An efficient Microcode Compiler for Application Specific DSP Processors," IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 9, pp. 925-937, September 1990.
	5	K. K. Parhi, VLSI Digital Signal Processing, Design and Implementation, ch. 6. New York: Wiley & Sons, 1999.
	6	A. P. Chandrakasan and R. W. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits," Proceedings of the IEEE, vol. 83, pp. 498-523, April 1995.
	7	Renu Mehra , Lisa M. Guerra , Jan M. Rabaey, Low-power architectural synthesis and the impact of exploiting locality, Journal of VLSI Signal Processing Systems, v.13 n.2-3, p.239-258, Aug./Sept. 1996 [doi>10.1007/BF01130408]
	8	R. Mehra and J. Rabaey, "Exploiting Regularity for Low-Power Design," in Proc. IEEE Custom Integrated Circuits Conference, pp. 401-404, May 1996.
	9	T. Arslan and A. T. Erdogan, "Data Block Processing for Low Power Implementation of Direct Form FIR Filters On Single Multiplier CMOS DSPs," in Proceedings of ISCAS-98, (Monterey, CA, USA), June 1998.
	10	K. Masselos et al., "A Movel Methodology for Power Consumption Reduction in a Class of DSP Algorithms," in Proceedings of ISCAS- 98, (Monterey, CA, USA), June 1998.
	11	Anand Raghunathan , Niraj K. Jha, Behavioral Synthesis for low Power, Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, p.318-322, October 10-12, 1994
	12	M. Potkonjak, M. B. Srivastava, and A. P. Chandrakasan, "Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 151-165, February 1996.
	13	Keshab K. Parhi , David G. Messerschmitt, Static Rate-Optimal Scheduling of Iterative Data-Flow Programs Via Optimum Unfolding, IEEE Transactions on Computers, v.40 n.2, p.178-195, February 1991 [doi>10.1109/12.73588]
	14	C. E. Leiserson and J. B. Saxe, "Optimizing Synchronous Systems," Journal of VLSI and Computer Systems, vol. 1, no. 1, pp. 11-67, 1983.
	15	Michel X. Goemans , David P. Williamson, A General Approximation Technique for Constrained Forest Problems, SIAM Journal on Computing, v.24 n.2, p.296-317, April 1995 [doi>10.1137/S0097539793242618]
	16	K. K. Parhi, "Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation," IEEE Trans. Circuits And Systems II Analog and Digital Signal Processing, vol. 39, pp. 423-440, July 1992.
	17	Alan V. Oppenheim , Ronald W. Schafer, Discrete-time signal processing, Prentice-Hall, Inc., Upper Saddle River, NJ, 1989
	18	Janardhan H. Satyanarayana , Keshab K. Parhi, HEAT: hierarchical energy analysis tool, Proceedings of the 33rd annual conference on Design automation, p.9-14, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240520]

CITED BY

Zili Shao , Qingfeng Zhuge , Meilin Liu , Chun Xue , Edwin H. M. Sha , Bin Xiao, Algorithms and analysis of scheduling for loops with minimum switching, International Journal of Computational Science and Engineering, v.2 n.1/2, p.88-97, June 2006

Collaborative Colleagues:

Vijay Sundararajan: colleagues

Keshab K. Parhi: colleagues

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