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A hybrid approach for core-based system-level power modeling
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Source Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents
Yokohama, Japan
Pages: 141 - 146  
Year of Publication: 2000
ISBN:0-7803-5974-7
Authors
Tony Givargis  Department of Computer Science and Engineering, University of California, Riverside, CA
Frank Vahid  Department of Computer Science and Engineering, University of California, Riverside, CA
Jörg Henkel  C&C Research Laboratories, NEC, 4 Independence Way, Princeton, NJ
Sponsors
IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 17,   Citation Count: 10
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references   cited by   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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J.Chern, J.Huang, L.Arledge, P.Li, P.Yang, Multilevel Metal Capacitance Models for CAD Design synthesis Systems, IEEE Electron Device Letters, vol. 13, no. 1, pp.32-34, January 1992.
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T.Kuhn, W.Rosenstiel, U.Kebschull, Object Oriented Hardware Modeling and Simulation Based on Java, International Workshop on IP Based Synthesis and System Design, Grenoble, France, 1998.
 
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B.Payne, Rapid Silicon Prototyping: Paradigm for Custom Systemon-a-Chip Design, http://www.vlsi.com/velocity, 1998.
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National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1997.

CITED BY  10
Collaborative Colleagues:
Tony Givargis: colleagues
Frank Vahid: colleagues
Jörg Henkel: colleagues