| A hybrid approach for core-based system-level power modeling |
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Asia and South Pacific Design Automation Conference
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Proceedings of the 2000 Asia and South Pacific Design Automation Conference
table of contents
Yokohama, Japan
Pages: 141 - 146
Year of Publication: 2000
ISBN:0-7803-5974-7
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Authors
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Tony Givargis
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Department of Computer Science and Engineering, University of California, Riverside, CA
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Frank Vahid
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Department of Computer Science and Engineering, University of California, Riverside, CA
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Jörg Henkel
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C&C Research Laboratories, NEC, 4 Independence Way, Princeton, NJ
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Downloads (6 Weeks): 1, Downloads (12 Months): 17, Citation Count: 10
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Anantha P. Chandrakasan , Miodrag Potkonjak , Jan Rabaey , Robert W. Brodersen, HYPER-LP: a system for power minimization using architectural transformations, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.300-303, November 1992, Santa Clara, California, United States
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Tony D. Givargis , Jörg Henkel , Frank Vahid, Interface and cache power exploration for core-based embedded system design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.270-273, November 07-11, 1999, San Jose, California, United States
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T.Kuhn, W.Rosenstiel, U.Kebschull, Object Oriented Hardware Modeling and Simulation Based on Java, International Workshop on IP Based Synthesis and System Design, Grenoble, France, 1998.
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Ganesh Lakshminarayana , Anand Raghunathan , Kamal S. Khouri , Niraj K. Jha , Sujit Dey, Common-case computation: a high-level technique for power and performance optimization, Proceedings of the 36th ACM/IEEE conference on Design automation, p.56-61, June 21-25, 1999, New Orleans, Louisiana, United States
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Claudio Passerone , Roberto Passerone , Claudio Sansoè , Jonathan Martin , Alberto Sangiovanni-Vincentelli , Rick McGeer, Modeling reactive systems in Java, Proceedings of the 6th international workshop on Hardware/software codesign, p.15-19, March 15-18, 1998, Seattle, Washington, United States
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B.Payne, Rapid Silicon Prototyping: Paradigm for Custom Systemon-a-Chip Design, http://www.vlsi.com/velocity, 1998.
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Anand Raghunathan , Sujit Dey , Niraj K. Jha, Glitch analysis and reduction in register transfer level power optimization, Proceedings of the 33rd annual conference on Design automation, p.331-336, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240581]
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James Shin Young , Josh MacDonald , Michael Shilman , Abdallah Tabbara , Paul Hilfinger , A. Richard Newton, Design and specification of embedded systems in Java using successive, formal refinement, Proceedings of the 35th annual conference on Design automation, p.70-75, June 15-19, 1998, San Francisco, California, United States
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National Technology Roadmap for Semiconductors, Semiconductor Industry Association, 1997.
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CITED BY 10
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J. A. Darringer , R. A. Bergamaschi , S. Bhattacharya , D. Brand , A. Herkersdorf , J. K. Morrell , I. Nair , P. Sagmeister , Y. Shin, Early analysis tools for system-on-a-chip design, IBM Journal of Research and Development, v.46 n.6, p.691-707, November 2002
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