Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

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Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 99 - 104

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Takahiro Deguchi	Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan
Tetsushi Koide	VLSI Design and Education Center, The University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, Tokyo 113-8656, Japan
Shin'ichi Wakabayashi	Faculty of Engineering, Hiroshima University, 4-1, Kagamiyama 1 chome, Higashi-Hiroshima, 739-8527, Japan

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 11, Citation Count: 2

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references cited by collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	"LOQO A system for solving linear and/or quadratic programing problems," Princeton University (1992).
	2	"TimberWolf 7.0 Macro/Standard Cell Floorplanning, Placement and Routing Package," Yale University (1996).
	3	H. B. Bakoglu: "Circuits, Interconnects, and Packaging for VLSI," Addison-Wesley (1990).
	4	R. E. Burkhard , U. Derigs, Assignment and Matching Problems: Solution Methods with FORTRAN-Programs, Springer-Verlag New York, Inc., Secaucus, NJ, 1980
	5	M. Burstein and R. Pelavin: "Hierarchical wire routing," IEEE Trans.CAD, vol.CAD-2, No.4, pp. 223-234 (1983).
	6	Chung-Ping Chen , Yao-Ping Chen , D. F. Wong, Optimal wire-sizing formula under the Elmore delay model, Proceedings of the 33rd annual conference on Design automation, p.487-490, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240611]
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	11	Robert C. Carden, IV , Chung-Kuan Cheng, A global router using an efficient approximate multicommodity multiterminal flow algorithm, Proceedings of the 28th conference on ACM/IEEE design automation, p.316-321, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127687]
	12	E. L. Lawler: "Combinatorial Optimization: Networks and Matroids," Holt, Rinehart and Winston (1976).
	13	John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin , Ching-Yen Ho, New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing, Proceedings of the 33rd annual conference on Design automation, p.395-400, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240594]
	14	E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton and A. Sangiovanni-Vincentelli: "SIS:A system for sequential circuit synthesis," Tech. Electronics Research Laboratory (1992).
	15	Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, Norwell, MA, 1993

CITED BY 2

	Shih-Ping Lin , Yao-Wen Chang, A novel framework for multilevel routing considering routability and performance, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.44-50, November 10-14, 2002, San Jose, California
	Tsung-Yi Ho , Yao-Wen Chang , Sao-Jie Chen , D. T. Lee, A Fast Crosstalk- and Performance-Driven Multilevel Routing System, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.382, November 09-13, 2003

Collaborative Colleagues:

Takahiro Deguchi: colleagues

Tetsushi Koide: colleagues

Shin'ichi Wakabayashi: colleagues

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