An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines

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An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines

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Asia and South Pacific Design Automation Conference archive
Proceedings of the 2000 Asia and South Pacific Design Automation Conference table of contents

Yokohama, Japan

Pages: 61 - 66

Year of Publication: 2000

ISBN:0-7803-5974-7

Authors

Riccardo Forth	University Halle-Wittenberg, Institute for Computer Science, Halle (Saale), D-06099, Germany
Paul Molitor	University Halle-Wittenberg, Institute for Computer Science, Halle (Saale), D-06099, Germany

Sponsors

IEEE-CAS : Circuits & Systems
IPSJ : Information Processing Society of Japan
SIGDA: ACM Special Interest Group on Design Automation
IEICE : Inst of Electronics, Info & Communication Engineers

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 0

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references collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Pranav Ashar , Sharad Malik, Fast functional simulation using branching programs, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.408-412, November 05-09, 1995, San Jose, California, United States
	2	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	3	J. Burch, E. Clarke, D. Long, K. McMillan, and D. Dill. Symbolic model checking for sequential circuit verification. IEEE Trans. on CAD, 13(4):401-424, 1994.
	4	O. Coudert, C. Berthet, and J.C. Madre. Verification of sequential machines using Boolean functional vectors. In Proceedings of IMEC-IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pages 111-128, 1989.
	5	Shi-Yu Huang , Kwant-Ting Cheng, Formal Equivalence Checking and Design DeBugging, Kluwer Academic Publishers, Norwell, MA, 1998
	6	Kenneth L. McMillan, Symbolic Model Checking, Kluwer Academic Publishers, Norwell, MA, 1993
	7	Chr. Meinel and T. Theobald. Local encoding transformations for optimizing OBDD-representations of finite state machines. Forschungsbericht 96-23, Fachbereich Mathematik und Informatik, Universitaet Trier, Germany, 1996.
	8	Christoph Meinel , Thorsten Theobald, On the Influence of the State Encoding on OBDD-Representations of Finite State Machines, Proceedings of the 22nd International Symposium on Mathematical Foundations of Computer Science, p.408-417, August 25-29, 1997
	9	Richard Rudell, Dynamic variable ordering for ordered binary decision diagrams, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.42-47, November 07-11, 1993, Santa Clara, California, United States
	10	Christoph Scholl , Rolf Drechsler , Bernd Becker, Functional simulation using binary decision diagrams, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.8-12, November 09-13, 1997, San Jose, California, United States
	11	Chr. Scholl, D. M~ller, P. Molitor, and R. Drechsler. BDD minimization using symmetries. IEEE Trans. on CAD, 18(2):81- 100, February 1999.
	12	H. Touati, H. Savoj, B. Lin, R. Brayton, and A. Sangiovanni- Vincentelli. Implicit state enumeration of finite state machines using BDDs. In IEEE Int'l Conf. on CAD, pages 130-133, 1990.

Collaborative Colleagues:

Riccardo Forth: colleagues

Paul Molitor: colleagues

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