A high performance RNS multiply-accumulate unit

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A high performance RNS multiply-accumulate unit

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 145 - 148

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

A. P. Preethy	Department of Computer Science, Georgia State University, 30 Pryor St., SE 750 Atlanta, GA
Damu Radhakrishnan	Department of Electrical and Computer Engineering, State University of New York, 75 S. Manheim Blvd., New Paltz, New York
Amos Omondi	School of Computer Engineering, Nanyang Technological, University, Nanyang Ave., Singapore 639798

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Michael A Soderstrand , W Kenneth Jenkins , Graham A Jullien , Fred J Taylor, Residue number system arithmetic: modern applications in digital signal processing, IEEE Press, Piscataway, NJ, 1986
	2	Preethy, A.P., and Radhakrishnan, D., "A 36-bit Balanced Moduli MAC Architecture," Proc. IEEE Midwest Symp. on Circuits and Systems, New Mexico, pp. 380-383, Aug. 1999.
	3	Vinogradov, I.M., Elements of Number Theory. New York: Dover, 1954.
	4	A. Drolshagen , H. Henkelmann , W. Anheier, Processor Elements for the Standard Cell Implementation of Residue Number Systems, Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, p.116, July 14-16, 1997
	5	Henkelmann, H., Drolshagen, A., Bagherinia, H., Ahrens, H., and Anheier, W., "Automated Implementation of RNS-to- Binary Converters," Proc. IEEE Int'l Symp. on Circuits and Systems, vol. 2, pp. 137-140, 1998.
	6	Hohne, R.A., and Siferd, R., "A Programmable High Performance Processor using the Residue Number System and CMOS VLSI Technology," Proc .IEEE National Aerospace and Electronics Conf., vol. 1, pp. 41-43, 1989.
	7	Barraclough, S.R., Sotheran, M., Burgin, K., Wise, A.P., Vadher, A., Robbins, W.P., and Forsyth, R.M., "The Design and Implementation of the IMS A110 Image and Signal Processor," Proc. IEEE Custom Integrated Circuits Conf., 1989.
	8	Izumikawa, M., Igura, H., Furuta, K., Ito, H., Wakabayashi, H., Nakajima, K., Mogami, T., Horiuchi, T., and Yamashina, M., "A 0.25-micron CMOS 0.9-v 100-MHz DSP Core," IEEE Journal of Solid-state circuits, vol. 32, no. 1, pp. 52- 61, Jan. 1997.
	9	Seung-M. Lee , Jin-H. Chung , Hying-S. Yoon , Mike M-O. Lee, High speed and ultra-low power 16×16 MAC deisgn using TG techniques for web-based multimedia system, Proceedings of the 2000 conference on Asia South Pacific design automation, p.17-18, January 2000, Yokohama, Japan [doi>10.1145/368434.368483]