Transistor sizing for reliable domino logic design in dual threshold voltage technologies

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Transistor sizing for reliable domino logic design in dual threshold voltage technologies

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 133 - 138

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

Seong-Ook Jung	Coordinated Science, Laboratory, ECE Department, University of Illinois at Urbana-Champaign
Ki-Wook Kim	Pluris, Inc., 10455 Bandley Dr., Cupertino, CA
Sung-Mo Steve Kang	Dean of Baskin School of engineering, University of California at Santa Cruz

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

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ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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