An efficient model for frequency-dependent on-chip inductance

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An efficient model for frequency-dependent on-chip inductance

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 115 - 120

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

Min Xu	ECE Department, University of Wisconsin-Madison, Madison, WI
Lei He	ECE Department, University of Wisconsin-Madison, Madison, WI

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 18, Citation Count: 9

Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Norman Chang , Shen Lin , Lei He , O. Sam Nakagawa , Weize Xie, Clocktree RLC extraction with efficient inductance modeling, Proceedings of the conference on Design, automation and test in Europe, p.522-526, March 27-30, 2000, Paris, France [doi>10.1145/343647.343838]
	2	Jason Cong , Lei He , Andrew B. Kahng , David Noice , Nagesh Shirali , Steve H.-C. Yen, Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology, Proceedings of the 34th annual conference on Design automation, p.627-632, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266303]
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	5	Kaushik Gala , Vladimir Zolotov , Rajendran Panda , Brian Young , Junfeng Wang , David Blaauw, On-chip inductance modeling and analysis, Proceedings of the 37th conference on Design automation, p.63-68, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337313]
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	14	Lawrence Pileggi, Coping with RC(L) interconnect design headaches, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.246-253, November 05-09, 1995, San Jose, California, United States
	15	X. Qi, G. Wang, Z. Yu, and R. W. Dutton. On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation. In Proc. IEEE Custom Integrated Circuits Conference, May 2000.
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CITED BY 9

	Jun Chen , Lei He, Determination of worst-case crosstalk noise for non-switching victims in GHz+ buses, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Amitava Bhaduri , Ranga Vemuri, Moment-driven coupling-aware routing methodology, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Shizhong Mei , Yehea I. Ismail, Modeling skin and proximity effects with reduced realizable RL circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.437-447, April 2004
	Tao Lin , Michael W. Beattie , Lawrence T. Pileggi, On the efficacy of simplified 2D on-chip inductance models, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Jun Chen , Lei He, Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Hao Yu , Lei He, Vector potential equivalent circuit based on PEEC inversion, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Sanjay Pant , Eli Chiprout, Power grid physics and implications for CAD, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Ahmed Shebaita , Dusan Petranovic , Yehea Ismail, Importance of volume discretization of single and coupled interconnects, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Sanjay Pant , Eli Chiprout , David Blaauw, Power Grid Physics and Implications for CAD, IEEE Design & Test, v.24 n.3, p.246-254, May 2007