Hierarchical model order reduction for signal-integrity interconnect synthesis

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Hierarchical model order reduction for signal-integrity interconnect synthesis

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 109 - 114

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

Yu-Min Lee	Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WI
Charlie Chung-Ping Chen	Department of Electrical and Computer Engineering, University of Wisconsin at Madison, Madison, WI

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 21, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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