Who are the alternative wires in your neighborhood? (alternative wires identification without search)

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Who are the alternative wires in your neighborhood? (alternative wires identification without search)

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 103 - 108

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

Chih-Wei Jim Chang	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA
Malgorzata Marek-Sadowska	Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 13, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Brayton, G. Hachtel, and A. Sangiovanni-Vincentelli, "Multilevel Logic Synthesis", Proc. IEEE, vol. 78, pp.264-300, Feb. 1990.
	2	Chih-Wei Chang , Chung-Kuan Cheng , Peter Suaris , Malgorzata Marek-Sadowska, Fast post-placement rewiring using easily detectable functional symmetries, Proceedings of the 37th conference on Design automation, p.286-289, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337420]
	3	C. -W. Chang and M. Marek-Sadowska, "Negative Thinking on Redundancy Addition and Removal", presented in Semiconductor Research Cooperation conference TECHCON, September, 2000
	4	S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, "Perturb and Simplify: Multi-level Boolean Network Optimizer", IEEE Trans. on CAD, vol. 15, Dec. 1996, p1494-1504
	5	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Circuit Optimization by Rewiring, IEEE Transactions on Computers, v.48 n.9, p.962-970, September 1999 [doi>10.1109/12.795224]
	6	Shih-Chieh Chang , Lukas P. P. P. van Ginneken , Malgorzata Marek-Sadowska, Fast Boolean optimization by rewiring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.262-269, November 10-14, 1996, San Jose, California, United States
	7	S. -C. Chang, K.-T. Cheng, N. S. Woo, and M. Marek-Sadowska, "Post-layout Logic Restructuring Using Alternative Wires', IEEE Trans. on Computer-Aided Design, vol. 6, pp. 587-596, June, 1997
	8	Ki-Seok Chung , C. L. Liu, Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction, Proceedings of the 1998 international symposium on Low power electronics and design, p.215-220, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280904]
	9	L. A. Entrena and K. -T. Cheng, "Combinational and Sequential Logic Optimization by Redundancy Addition and Removal", Trans. on Computer-Aided Design, 1995, pp. 909- 916
	10	C. R. Edwards and S. L. Hurst, "A Digital Synthesis Procedure under Function Symmetries and Mapping Methods', IEEE Trans. on Computers, C-27(11), 985-997, Nov. 1978
	11	Ric Chung-Yang Huang , Yucheng Wang , Kwang-Ting Chen, LIBRA—a library-independent framework for post-layout performance optimization, Proceedings of the 1998 international symposium on Physical design, p.135-140, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274555]
	12	Mahesh A. Iyer , Miron Abramovici, FIRE: a fault-independent combinational redundancy identification algorithm, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.4 n.2, p.295-301, June 1996 [doi>10.1109/92.502203]
	13	Yi-Min Jiang , Angela Krstic , Kwang-Ting Cheng , Malgorzata Marek-Sadowska, Post-layout logic restructuring for performance optimization, Proceedings of the 34th annual conference on Design automation, p.662-665, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266313]
	14	W. Kunz.and D. Pradhan, "Recursive Learning: A New Implication Technique for Efficient Solutions to CAD Problems: Test, Verification and Optimization", IEEE Trans. on CAD, pp 1143-1158, Sept. 1994
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	16	Shipra Panda , Fabio Somenzi, Who are the variables in your neighborhood, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.74-77, November 05-09, 1995, San Jose, California, United States
	17	Subarnarekha Sinha , Robert K. Brayton, Implementation and use of SPFDs in optimizing Boolean networks, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.103-110, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288584]
	18	K.-H. Tsai , R. Tompson , J. Rajski , M. Marek-Sadowska, STAR-ATPG: A High Speed Test Pattern Generator for Large Scan Designs, Proceedings of the 1999 IEEE International Test Conference, p.1021, September 28-30, 1999
	19	Yu-Liang Wu , Wangning Long , Hongbing Fan, A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks, Proceedings of the 13th International Conference on VLSI Design, p.268, January 04-07, 2000
	20	K. McElvain, "LGSynth93 Benchmark Set: Version 4.0", http://zodiac.cbl.ncsu.edu/CBL_Docs/lgs93.html

CITED BY 2

	S. Chatterjee , A. Mishchenko , R. Brayton , X. Wang , T. Kam, Reducing structural bias in technology mapping, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.519-526, November 06-10, 2005, San Jose, CA
	Catherine L. Zhou , Wai-Chung Tang , Wing-Hang Lo , Yu-Liang Wu, How much can logic perturbation help from netlist to final routing for FPGAs, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California