2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test

Full text

Pdf (635 KB)

Source

Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 93 - 96

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

Seung-Moon Yoo	ECE Department, University of Illinois at Urbana-Champaign
Seong-Ook Jung	ECE Department, University of Illinois at Urbana-Champaign
Sung-Mo Steve Kang	Baskin School of Engineering, University of California at Santa Cruz

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 0

Additional Information:

references index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/368122.368874 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. P. Stroele and H. J. Wunderlich. Hardware-Optimal Test Register Insertion. In IEEE Transactions on Computer-Aided Design, pages 531-540, 1998.
	2	Srivaths Ravi , Ganesh Lakshminarayana , Niraj K. Jha, TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST, Proceedings of the 1999 17TH IEEE VLSI Test Symposium, p.398, April 26-30, 1999
	3	Danial J. Neebel , Charles R. Kime, Cellular Automata for Weighted Random Pattern Generation, IEEE Transactions on Computers, v.46 n.11, p.1219-1229, November 1997 [doi>10.1109/12.644297]
	4	Danial J. Neebel , Charles R. Kime, Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation, Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them, p.1013-1022, October 17-21, 1993
	5	Sybille Hellebrand , Birgit Reeb , Steffen Tarnick , Hans-Joachim Wunderlich, Pattern generation for a deterministic BIST scheme, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.88-94, November 05-09, 1995, San Jose, California, United States
	6	Nur A. Touba , Edward J. McCluskey, Altering a Pseudo-Random Bit Sequence for Scan-Based BIST, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.167-175, October 20-25, 1996
	7	Hans-Joachim Wunderlich , Gundolf Kiefer, Bit-flipping BIST, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.337-343, November 10-14, 1996, San Jose, California, United States
	8	Paul H. Bardell , William H. McAnney , Jacob Savir, Built-in test for VLSI: pseudorandom techniques, Wiley-Interscience, New York, NY, 1987
	9	B. Koenemann. LFSR-Coded Test Patterns for Scan Designs. In Proe. of European Test Conference, pages 237--242, 1991.
	10	http://www.crhc.uiuc.edu/IGATE/hitec software.html.
	11	Douglas Kay and Samiha Mourad. Controllable LFSR BIST. In Proc. of Instrumentation and Measurement Technology Conference, pages 223--228, 2000.