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A circuit level implementation of an adaptive issue queue for power-aware microprocessors
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Source Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents
West Lafayette, Indiana, United States
Pages: 73 - 78  
Year of Publication: 2001
ISBN:1-58113-351-0
Authors
Alper Buyuktosunoglu  University of Rochester, Electrical and Computer Engineering, Rochester, NY
David Albonesi  University of Rochester, Electrical and Computer Engineering, Rochester, NY
Stanley Schuster  IBM T. J. Watson Research Center, Yorktown Heights, NY
David Brooks  IBM T. J. Watson Research Center, Yorktown Heights, NY
Pradip Bose  IBM T. J. Watson Research Center, Yorktown Heights, NY
Peter Cook  IBM T. J. Watson Research Center, Yorktown Heights, NY
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 25,   Citation Count: 16
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
David H. Albonesi, Dynamic IPC/clock rate optimization, Proceedings of the 25th annual international symposium on Computer architecture, p.282-292, June 27-July 02, 1998, Barcelona, Spain
 
2
D. H. Albonesi. The Inherent Energy Efficiency of Complexity-Adaptive Processors. Proc. ISCA Workshop on Power-Driven Microarchitecture, June 1998.
3
Rajeev Balasubramonian , David Albonesi , Alper Buyuktosunoglu , Sandhya Dwarkadas, Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.245-257, December 2000, Monterey, California, United States  [doi>10.1145/360128.360153]
4
Michael Butler , Yale Patt, An investigation of the performance of various dynamic scheduling techniques, Proceedings of the 25th annual international symposium on Microarchitecture, p.1-9, December 01-04, 1992, Portland, Oregon, United States
 
5
G. Cai. Architectural level power/performance optimization and dynamic power estimation. Proc. of the Cool Chips Tutorial, in conjunction with Micro-32, 1999.
6
Ramon Canal , Antonio González, A low-complexity issue logic, Proceedings of the 14th international conference on Supercomputing, p.327-335, May 08-11, 2000, Santa Fe, New Mexico, United States  [doi>10.1145/335231.335263]
 
7
Daniel Marcos Chapiro, Globally-asynchronous locally-synchronous systems (performance, reliability, digital), 1985
 
8
D. Folegnani and A. Gonzalez. Reducing the power consumption of the issue logic. Proc. ISCA Workshop on Complexity-Effective Design, June 2000.
 
9
R. E. Kessler, The Alpha 21264 Microprocessor, IEEE Micro, v.19 n.2, p.24-36, March 1999  [doi>10.1109/40.755465]
10
Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
11
Michael Powell , Se-Hyun Yang , Babak Falsafi , Kaushik Roy , T. N. Vijaykumar, Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories, Proceedings of the 2000 international symposium on Low power electronics and design, p.90-95, July 25-27, 2000, Rapallo, Italy  [doi>10.1145/344166.344526]
 
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C. L.Seitz. System Timing. In Carver A. Mead and Lynn A. Conway, editors, Introduction to VLSI Systems, chapter 7, Addison-Wesley, 1980.
 
13
Allen E. Sjogren , Chris J. Myers, Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline, Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), p.47, September 15-16, 1997
 
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K. Wilcox and S. Manne. Alpha Processors: A history of power issues and a look to the future. Proc. of the Cool Chips Tutorial, in conjunction with Micro-32, 1999.
 
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Kenneth C. Yeager, The MIPS R10000 Superscalar Microprocessor, IEEE Micro, v.16 n.2, p.28-40, April 1996  [doi>10.1109/40.491460]
 
16
AS/X User's Guide. IBM Corporation, New York, 1996.

CITED BY  16
Tejas Karkhanis , James E. Smith , Pradip Bose, Saving energy with just in time instruction delivery, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
Dmitry Ponomarev , Gurhan Kucuk , Kanad Ghose, Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
Alper Buyuktosunoglu , Tejas Karkhanis , David H. Albonesi , Pradip Bose, Energy efficient co-adaptive instruction fetch and issue, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
David H. Albonesi , Rajeev Balasubramonian , Steven G. Dropsho , Sandhya Dwarkadas , Eby G. Friedman , Michael C. Huang , Volkan Kursun , Grigorios Magklis , Michael L. Scott , Greg Semeraro , Pradip Bose , Alper Buyuktosunoglu , Peter W. Cook , Stanley E. Schuster, Dynamically Tuning Processor Resources with Adaptive Processing, Computer, v.36 n.12, p.49-58, December 2003
Joseph J. Sharkey , Dmitry V. Ponomarev , Kanad Ghose , Oguz Ergin, Instruction packing: reducing power and delay of the dynamic scheduling logic, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
Jinson Koppanalil , Prakash Ramrakhyani , Sameer Desai , Anu Vaidyanathan , Eric Rotenberg, A case for dynamic pipeline scaling, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
Houman Homayoun , Sudeep Pasricha , Mohammad Makhzan , Alex Veidenbaum, Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors, ACM SIGPLAN Notices, v.43 n.7, July 2008
Steven Dropsho , Greg Semeraro , David H. Albonesi , Grigorios Magklis , Michael L. Scott, Dynamically Trading Frequency for Complexity in a GALS Microprocessor, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.157-168, December 04-08, 2004, Portland, Oregon
Chengmo Yang , Alex Orailoglu, Power-efficient instruction delivery through trace reuse, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
Joseph J. Sharkey , Dmitry V. Ponomarev , Kanad Ghose , Oguz Ergin, Instruction packing: Toward fast and energy-efficient instruction scheduling, ACM Transactions on Architecture and Code Optimization (TACO), v.3 n.2, p.156-181, June 2006
Albert Meixner , Daniel J. Sorin, Unified microprocessor core storage, Proceedings of the 4th international conference on Computing frontiers, May 07-09, 2007, Ischia, Italy
Dmitry Ponomarev , Gurhan Kucuk , Kanad Ghose, Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency, IEEE Transactions on Computers, v.55 n.2, p.199-213, February 2006
Joseph Sharkey , Deniz Balkan , Dmitry Ponomarev, Adaptive reorder buffers for SMT processors, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
Chung-Ho Chen , Kuo-Su Hsiao, Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality, IEEE Transactions on Computers, v.56 n.11, p.1534-1548, November 2007
Joseph J. Sharkey , Dmitry V. Ponomarev, Exploiting Operand Availability for Efficient Simultaneous Multithreading, IEEE Transactions on Computers, v.56 n.2, p.208-223, February 2007
Yu-Lai Zhao , Xian-Feng Li , Dong Tong , Xu Cheng, An energy-efficient instruction scheduler design with two-level shelving and adaptive banking, Journal of Computer Science and Technology, v.22 n.1, p.15-24, January 2007

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.3 Microcomputers
          Subjects: Microprocessors

  H. Information Systems
  H.3 INFORMATION STORAGE AND RETRIEVAL
      H.3.3 Information Search and Retrieval
          Subjects: Retrieval models


General Terms:
Algorithms, Design, Performance

Collaborative Colleagues:
Alper Buyuktosunoglu: colleagues
David Albonesi: colleagues
Stanley Schuster: colleagues
David Brooks: colleagues
Pradip Bose: colleagues
Peter Cook: colleagues

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