An accurate evaluation of routing density for symmetrical FPGAs

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An accurate evaluation of routing density for symmetrical FPGAs

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 51 - 55

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

Nak-Woong Eum	Electronics & Telecommunications Res. Institute, Taejon, Korea
Taewhan Kim	Dept. of EECS, KAIST, Taejon, Korea
Chong-Min Kyung	Dept. of EECS, KAIST, Taejon, Korea

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	The Programmable Gate Array Data Book, Xilinx Inc., San Jose, CA, 1999.
	2	S. Brown, J. Rose, and Z. G. Vranesic, "A detailed router for field-programmable gate arrays," IEEE Trans. on Computer-Aided Design, 11(5):620-628, May 1992.
	3	F. D. Lewis , Wang Chia-Chi Pong, A negative reinforcement method for PGA routing, Proceedings of the 30th international conference on Design automation, p.601-605, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165064]
	4	G. G. Lemieux and S. D. Brown, "A detailed routing algorithm for allocating wire segments in field-programmable gate arrays," ACM/SIGDA Physical Design Workshop, pp.215-226, 1993.
	5	Y.-L. Wu and M. Marek-Sadowska, "An efficient router for 2-D field-programmable gate arrays," Proc. of European Design and Test Conference, pp.412-416, 1994.
	6	Michael J. Alexander , Gabriel Robins, New performance-driven FPGA routing algorithms, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.562-567, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217589]
	7	Yachyang Sun , C. L. Liu, Routing in a new 2-dimensional FPGA/FPIC routing architecture, Proceedings of the 31st annual conference on Design automation, p.171-176, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196327]
	8	Yachyang Sun , Ting-Chi Wang , C. K. Wong , C. L. Liu, Routing for symmetric FPGAs and FPICs, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.486-490, November 07-11, 1993, Santa Clara, California, United States
	9	C.-D. Chen, Y.-S Lee, A. C.-H. Wu, and Y.-L. Lin, "TRACER-fpga: A router for RAM-based FPGA's," IEEE Trans. on Computer-Aided Design, 14(3):371-374, Match 1995.
	10	Y.-S. Lee and A. C.-H. W'u, "A performance and routability-driven router for FPGA's considering path delays," IEEE Trans. on Computer-Aided Design, 16(2):179-185, February 1997.
	11	T. Ohtsuki, "Maze-running and line-search algorithm," Layout and Design Versification, pp.99-131, North-Holland, 1985.
	12	J. Rose and S. Brown, "Flexibility of interconnection structures for field-programmable gate arrays," IEEE J. of Solid-State Circuits, 26(3):277-282, 1991.
	13	C. Y. Lee, "An algorithm for path connections and its application," IRE Trans. on Electronic Comput., EC-10:346-365, Sept. 1961.
	14	Marek Kubale , Boguslaw Jackowski, A generalized implicit enumeration algorithm for graph coloring, Communications of the ACM, v.28 n.4, p.412-418, April 1985 [doi>10.1145/3341.3350]
	15	Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997