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ITEM: an iterative improvement test generation procedure for synchronous sequential circuits

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Great Lakes Symposium on VLSI archive
Proceedings of the 11th Great Lakes symposium on VLSI table of contents

West Lafayette, Indiana, United States

Pages: 13 - 18

Year of Publication: 2001

ISBN:1-58113-351-0

Authors

Irith Pomeranz	School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN
Sudhakar M. Reddy	Electrical & Computer Eng. Dept., University of Iowa, Iowa City, IA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	T.P. Kelsey and K. K. Saluja, "Fast Test Generation for Sequential Circuits", Intl. Conf. Comp. Aided Design, Nov. 1989, pp. 354-357.
	4	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
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	7	X. Lin, I. Pomeranz and S. M. Reddy, "MIX : A Test Generation System for Synchronous Sequential Circuits", submitted to Intl. Conf. on Computer-Aided Design, 1997.
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	16	Tatiana Orenstein , Zvi Kohavi , Irith Pomeranz, An optimal algorithm for cycle breaking in directed graphs, Journal of Electronic Testing: Theory and Applications, v.7 n.1-2, p.71-81, Aug./Oct. 1995 [doi>10.1007/BF00993315]
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