ACM Home Page
Please provide us with feedback. Feedback
Efficient finite field digital-serial multiplier architecture for cryptography applications
Full text PdfPdf (22 KB)
Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Munich, Germany
Page: 812  
Year of Publication: 2001
ISBN:0-7695-0993-2
Authors
G. Bertoni  Politechnico di Milano, P.zza L. Da Vinci n. 32, I-20133 Milano, Italy
L. Breveglieri  Politechnico di Milano, P.zza L. Da Vinci n. 32, I-20133 Milano, Italy
P. Fragneto  ST Mircroelectronics Agrate Brianza(MI), Via Olivetti 2, I-20041 Agrate B., Italy
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 14,   Downloads (12 Months): 32,   Citation Count: 0
Additional Information:

references   index terms   collaborative colleagues  

Tools and Actions: Review this Article  

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
C. Paar, "Implementation Options for Finite Fields Arithmetic for Elliptic Curve Cryptosystems", Proc. of 3 rd Workshop on Elliptic Curve Cryptosystems, ECC '99, Waterloo, Ontario, Canada, November, 1999
 
3
 
4
 
5
 
6
G. Bertoni, L. Breveglieri, L. Cantini, P. Fragneto, "Efficient Digit-Serial Recoded Multiplier Architecture for Galois Fields' Int. Rep. n.2000.46, Politecnico di Milano, Milano, Italy, December, 2000

Collaborative Colleagues:
G. Bertoni: colleagues
L. Breveglieri: colleagues
P. Fragneto: colleagues