ACM Home Page
Please provide us with feedback. Feedback
Low-power systems on chips (SOCs)
Full text PdfPdf (94 KB)
Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Munich, Germany
Page: 488  
Year of Publication: 2001
ISBN:0-7695-0993-2
Authors
C. Piguet  CSEM, Rue Jaquet-Droz 1, P.O. Box CH-2007 Neuchâtel
M. Renaudin  Laboratoire TIMA, 46 Avenue Félix Viallet, F-38031 Grenoble Cédex
T. Omnés  Interuniversity Micro-Electronics Centre(IMEC), Kapeldreef 75, B-3001 Leuven
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association
Publisher
IEEE Press  Piscataway, NJ, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 17,   Citation Count: 0
Additional Information:

references   index terms   collaborative colleagues  

Tools and Actions: Review this Article  

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
E. Brockmeyer, J. D'Eer, N. Busa, F. Catthoor, P. Lippens, and J. Huiskens. Code transformations for reduced data transfer and storage in low power realization of DAB synchro core. In Proc. PATMOS'99, Kos, Greece, 1999.
3
 
4
 
5
E. Brockmeyer, S. Wuytack, A. Vandecappelle, and F. Catthoor. Low power storage for hierarchical graphs. In Proc. 3rd ACM/IEEE Design and Test in Europe Conf. (DATE), Paris, France, Mar. 2000.
 
6
Cadence Design Systems. Cierto virtual component codesign (VCC) environment. http://www.cadence.com/datasheets/vcc environment.html , 2000.
 
7
F. Catthoor, K. Danckaert, C. Kulkarni, and T. J.-F. Omnes. Data transfer and storage architecture issues and exploration in modern DSPs. In Y. H. Yu, editor, Programmable Digital Signal Processors: Architecture, Programming, and Applications. Marcel Dekker, Inc., New York, USA, Dec. 2000.
 
8
 
9
 
10
 
11
Coware. Coware N2C design system overview. http://www.coware.com/, 2000.
 
12
 
13
 
14
R. Ginosar et al. Adaptive synchronization. In Proc. AINT 2000, Delft, Netherlands, July 18-20 2000.
 
15
V. Gutnik and A. Chandrakasan et al. Active GHz clock network using distributed PLLs. In Proc. IEEE Int. Solid-state Circuits Conf. (ISSCC), San Francisco, USA, Feb. 2000.
 
16
A. Jerraya. Hardware/software codesign. In Summer Course, Orebro, Sweden, August 14-16, 2000.
 
17
C. Kulkarni. Cache optimization for multimedia applications. PhD thesis, ESAT, EE Department, Katholieke Universiteit, Leuven, Belgium, Feb. 2001.
 
18
 
19
 
20
S. M. Nowick, M. B. Josepphs, and C. H. V. Berkel. Special Issue of the Proceedings of the IEEE on "Asynchronous Circuits and Systems". Feb. 1999.
21
 
22
T. J.-F. Omnes. Acropolis: a System-Level Precompiler for Data Transfer and Storage Exploration (DTSE) in High- Throughput Embedded System Design. Ph.D dissertation in Real-time Systems, Automation and Robotics, Centre de Recherche en Informatique de l'Ecole Nationale Superieure des Mines, Paris, France, May 2001.
 
23
T. J.-F. Omnes. Space-time memory access patterns: a step towards the object-oriented design of low-cost distributed platforms. In 5th Int. Wsh. on Software and COmPilers for Embedded Systems (SCOPES), St Goar, Germany, March 20-22, 2001.
 
24
C. Piguet. Parallelism and low-power. In Proc. Symp. Architectures de Machines (SymA'99), Rennes, France, June 8, 1999.
 
25
 
26
J. Robinson. Efficient general-purpose image compression with binary tree predictive coding. IEEE Trans. on Image Processing, 6(4):601-608, Apr. 1997.
 
27
Sematech. SIA rodmap. http://notes.sematech.org/ntrs/rdmpmem.nsf, 1997.
 
28
 
29
C. Ussery. Configurable Platforms: The ASIC Revolution. In Invited talk, 37th ACM/IEEE Design Automation Conf. (DAC), Los Angeles, USA, June 2000.
 
30
M. van Swaaij, F. Franssen, F. Catthoor, and H. de Man. Modeling data and control flow for high-level memory management. In Proc. 3rd ACM/IEEE European Design Automation Conf. (EDAC), pages 8-13, Brussels, Belgium, Mar. 1992.
31
32
 
33

Collaborative Colleagues:
C. Piguet: colleagues
M. Renaudin: colleagues
T. Omnés: colleagues