Architecture driven partitioning

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Architecture driven partitioning

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 479 - 487

Year of Publication: 2001

ISBN:0-7695-0993-2

Authors

J. Küter	Infineon Technologies AG, MP TI CS ATS, D-81541 Munich, Germany
E. Barke	Institute of Microelectronic Systems, University of Hannover, D-30167 Hannover, Germany

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Varghese, J.: "An Efficient Logic Emulation System", in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, No. 2, June 1993, pp. 171-174.
	3	Harbich, K.; Hoffmann, H.; Barke, E.: "A New Hierarchical Graph Model for Multiple FPGA Partitioning", Proceedings of WDTA, June 1998.
	4	Dirk Behrens , Klaus Harbich , Erich Barke, Hierarchical partitioning, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.470-477, November 10-14, 1996, San Jose, California, United States
	5	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	6	C. Lee, "An Algorithm for Path Connections and its Applications", IRE Transactions on Electronic Computers, Sept. 1961, pp. 346-365.
	7	George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266273]
	8	EDIF Version 2 0 0. EIA Interim Standard No. 44, 1987.
	9	Koch, G.; Kebschull, U.; Rosenstiel, W.: 'The Weaver Prototyping Environment for Hardware/Software Co-Design and Co-Debugging", DATE 98, Designer Track, Paris, 1998.
	10	Babb, J. et al.: "Logic Emulation with Virtual Wires", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 6, 1997, S. 609-626.