HALOTIS

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

Full text

Pdf (110 KB)

Source

Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 467 - 471

Year of Publication: 2001

ISBN:0-7695-0993-2

Authors

P. Vazquez	Instituto de Microelectronica de Sevilla. CNM, Edificio CICA, Avda/Reina Mercedes s/n 41012-Sevilla, Spain and Dpto. de Tecnologia Electronica., Universidad de Sevilla
J. Juan-Chico	Instituto de Microelectronica de Sevilla. CNM, Edificio CICA, Avda/Reina Mercedes s/n 41012-Sevilla, Spain and Dpto. de Tecnologia Electronica. Universidad de Sevilla
M. Bellido	Instituto de Microelectronica de Sevilla. CNM, Edificio CICA, Avda/Reina Mercedes s/n 41012-Sevilla, Spain and Dpto. de Tecnologia Electronica. Universidad de Sevilla
A. Acosta	Instituto de Microelectronica de Sevilla. CNM, Edificio CICA, Avda/Reina Mercedes s/n 41012-Sevilla, Spain and Dpto. de Electronica y Electromagnetismo. Universidad de Sevilla
M. Valencia	Instituto de Microelectronica de Sevilla. CNM, Edificio CICA, Avda/Reina Mercedes s/n 41012-Sevilla, Spain and Dpto. de Tecnologia Electronica. Universidad de Sevilla

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L. Bisdounis, S. Nikolaidis, O. Koufopavlou. "Analytical Transient Response and Propagation Delay Evaluation of the CMOS Inverter for Short-Channel Devices". IEEE J. of Solid-State Circ. pp. 302-306. Vol. 33, no. 2, Feb. 1998.
	2	J.M. Daga, D. Auvergne. "A Comprehensive Delay Macro Modeling for Submicrometer CMOS Logics". IEEE J. of Solid State Circuits. Vol. 34, No. 1, Jan. 1999.
	3	A.I. Kayssi, K.A. Sakallah, T.N. Mudge. "The Impact of Signal Transition Time on Path Delay Computation". IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 40, No. 5, pp. 302-309, May 1993.
	4	D. Auvergne, N. Azemard, D. Deschacht, M. Robert. "Input Waveform Slope Effects in CMOS Delays". IEEE J. of Solid-State Circ., Vol. 25, No. 6, pp. 1588-1590. Dec. 1990
	5	E. Melcher, W. R~thig, M. Dana. "Multiple Input Transitions in CMOS Gates". Microprocessing and Microprogramming 35 (1992) pp. 683-690. North Holland.
	6	C. Metra, M. Favalli, B. Ricc~. "Glitch power dissipation model". In Proc. PATMOS'95. pp. 175-189
	7	M. Eisele, J. Berthold. "Dynamic Gate Delay Modeling for Accurate Estimation of Glitch Powe at Logic Level". In Proc. PATMOS'95. pp. 190-201.
	8	Stephen H. Unger, The essence of logic circuits, Prentice-Hall, Inc., Upper Saddle River, NJ, 1989
	9	L.R. Marino. "General Theory of Metastable Operation". IEEE Trans. on Computers, C-30 n.2, pp. 107-115, Feb. 1981.
	10	L. Kleeman, A. Cantoni. "Metastable Behavior in Digital Systems", IEEE Design and Test of Computers, vol. 4. Dec. 1987
	11	L.M. Reyneri, L.M. del Corso, B. Sacco. "Oscillatory Metastability in Homogeneous and Inhomogeneous Flip-flops". IEEE J. of Solid-State Circ. Vol.25. n.1. Feb. 1990.
	12	J. Calvo, M. Valencia, J.L. Huertas. "Metastable Operation in RS Flip-flops". Int. J. Electronics, Vol. 70 n.6. 1991.
	13	D. Rabe, B. Fiuczynski, L. Kruse, A. Welslau, W. Nebel. "Comparison of Different Gate Level Glitch Models". In Proc. PATMOS'96. pp. 167-176.
	14	J. Juan-Chico, P. Ruiz-de-Clavijo, M.J. Bellido, A.J. Acosta, M. Valencia. "Inertial and degradation delay model for CMOS logic gates". In Proc. IEEE International Symposium on Circuits and Systems (ISCAS) 2000, pp. I-459-462, Geneva, May 2000.
	15	Jorge Juan-Chico , Manuel J. Bellido , Paulino Ruiz-de-Clavijo , Antonio J. Acosta , Manuel Valencia, Degradation Delay Model Extension to CMOS Gates, Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, p.149-158, September 13-15, 2000
	16	J. Juan-Chico, M.J. Bellido, A.J. Acosta, A. Barriga, M. Valencia. "Delay degradation effect in submicronic CMOS inverters". In Proc. PATMOS'97. pp. 215-224. Louvain-la-Neuve, Belgium, 1997.
	17	M.J. Bellido, J. Juan-Chico, A.J. Acosta, M. Valencia and J.L. Huertas. "Logical modelling of delay degradation effect in static CMOS gates". IEE Proceedings, Circuits, Devices and Systems, Vol. 147, No. 2, pp. 107-117. April 2000.