On the impact of on-chip inductance on signal nets under the influence of power grid noise

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On the impact of on-chip inductance on signal nets under the influence of power grid noise

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 451 - 459

Year of Publication: 2001

ISBN:0-7695-0993-2

Author

T. Chen

Systems VLSI Technology Organization, Hewlett-Packard Company, Fort Collins, CO

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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