Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding

Full text

Pdf (122 KB)

Source

Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 145 - 149

Year of Publication: 2001

ISBN:0-7695-0993-2

Authors

A. Chandra	Department of Electrical and Computer Engineering, Duke University, Durham, NC
K. Chakrabarty	Department of Electrical and Computer Engineering, Duke University, Durham, NC

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 4, Citation Count: 5

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Yervant Zorian , Erik Jan Marinissen , Sujit Dey, Testing embedded-core based system chips, Proceedings of the 1998 IEEE International Test Conference, p.130, October 18-22, 1998
	2	Vikram Iyengar , Krishnendu Chakrabarty , Brian T. Murray, Deterministic Built-in Pattern Generation for Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.15 n.1-2, p.97-114, August-October 1999 [doi>10.1023/A:1008384201996]
	3	Abhijit Jas , Nur A. Touba, Test vector decompression via cyclical scan chains and its application to testing core-based designs, Proceedings of the 1998 IEEE International Test Conference, p.458-464, October 18-22, 1998
	4	Ilker Hamzaoglu , Janak H. Patel, Test set compaction algorithms for combinational circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.283-289, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288615]
	5	S. W. Golomb, "Run-length encoding", IEEE Trans. Inf. Theory, vol. IT-12, pp. 399-401, 1966.
	6	H. Kobayashi and L. R. Bahl, "Image data compression by predictive coding, Part I: Prediction Algorithm", IBM Journal of R&D, vol. 18, pp. 164, 1974.
	7	Anshuman Chandra , Krishnendu Chakrabarty, Test Data Compression for System-on-a-Chip Using Golomb Codes, Proceedings of the 18th IEEE VLSI Test Symposium (VTS'00), p.113, April 30-May 04, 2000
	8	A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression architectures based on Golomb codes", IEEE Trans. CAD, vol. 20, March 2001 (accepted for publication).
	9	Hyung Ki Lee , Dong Sam Ha, An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.946-955, October 26-30, 1991
	10	D. Heidel , S. Dhong , P. Hofstee , M. Immediato , K. Nowka , J. Silberman , K. Stawiasz, 11.1 High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor, Proceedings of the 16th IEEE VLSI Test Symposium, p.234, April 26-30, 1998
	11	H. K. Lee and D. S. Ha. "On the Generation of Test Patterns for Combinational Circuits" Tech. Report No. 12 93, Dept. Electrical Eng., Virginia Poly. Inst. and State Univ.

CITED BY 5

	Anshuman Chandra , Krishnendu Chakrabarty, Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes, IEEE Transactions on Computers, v.52 n.8, p.1076-1088, August 2003
	Anshuman Chandra , Krishnendu Chakrabarty, Test Resource Partitioning for SOCs, IEEE Design & Test, v.18 n.5, p.80-91, September 2001
	Abhijit Jas , Bahram Pouya , Nur A. Touba, Test data compression technique for embedded cores using virtual scan chains, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.775-780, July 2004
	Carl Barnhart , Vanessa Brunkhorst , Frank Distler , Owen Farnsworth , Andrew Ferko , Brion Keller , David Scott , Bernd Koenemann , Takeshi Onodera, Extending OPMISR beyond 10x Scan Test Efficiency, IEEE Design & Test, v.19 n.5, p.65-72, September 2002
	Abhijit Jas , Nur A. Touba, Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor, Journal of Electronic Testing: Theory and Applications, v.18 n.4-5, p.503-514, August-October 2002