Deterministic software-based self-testing of embedded processor cores

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Deterministic software-based self-testing of embedded processor cores

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Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents

Munich, Germany

Pages: 92 - 96

Year of Publication: 2001

ISBN:0-7695-0993-2

Authors

A. Paschalis	Department of Informatics, University of Athens, Greece
D. Gizopoulos	Department of Infromatics, University of Piraeus, Greece
N. Kranitis	II&T, NCSR 'Demokritos', Athens, Greece
M. Psarakis	II&T, NCSR 'Demokritos', Athens, Greece
Y. Zorian	Logic Vision, San Jose, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
ECSI :
IEEE-CS\DATC : IEEE Computer Society
RAS : RAS
EDAC : Electronic Design Automation Consortium
IEEE-CS\TTTC : Test Technology Technical Council
IFIP WG 10.5 : IFIP WG 10.5
EDAA : European Design Automation Association

Publisher

IEEE Press Piscataway, NJ, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 6, Citation Count: 4

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	ARM9TDMI, Technical Reference Manual, Nov. 1998.
	2	V.D.Agrawal et al., "BIST for Digital Integrated Circuits", AT&T Tech. Journal, March 1994, pp. 30.
	3	Jian Shen , Jacob A. Abraham, Native mode functional test generation for processors with applications to self test and design validation, Proceedings of the 1998 IEEE International Test Conference, p.990-999, October 18-22, 1998
	4	Ken Batcher , Christos Papachristou, Instruction Randomization Self Test For Processor Cores, Proceedings of the 1999 17TH IEEE VLSI Test Symposium, p.34, April 26-30, 1999
	5	K.Radecka, J.Rajski, J. Tyszer, "Arithmetic built-in selftest for DSP cores," IEEE Trans. on CAD, vol.16, no.11, Nov. 1997, pp. 1358-1369.
	6	Janusz Rajski , Jerzy Tyszer, Arithmetic built-in self-test for embedded systems, Prentice-Hall, Inc., Upper Saddle River, NJ, 1998
	7	Sybille Hellebrand , Hans-Joachim Wunderlich , Andre Hertwig, Mixed-Mode BIST Using Embedded Processors, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.195-204, October 20-25, 1996
	8	Rainer Dorsch , Hans-Joachim Wunderlich, Accumulator based deterministic BIST, Proceedings of the 1998 IEEE International Test Conference, p.412-421, October 18-22, 1998
	9	Li Chen , Sujit Dey , Pablo Sanchez , Krishna Sekar , Ying Cheng, Embedded hardware and software self-testing methodologies for processor cores, Proceedings of the 37th conference on Design automation, p.625-630, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337599]
	10	Dimitris Gizopoulos , Antonis Paschalis , Yervant Zorian, An Effective Built-In Self-Test Scheme for Parallel Multipliers, IEEE Transactions on Computers, v.48 n.9, p.936-950, September 1999 [doi>10.1109/12.795222]
	11	Dimitris Gizopoulos , Antonis Paschalis , Yervant Zorian, Effective Built-In Self-Test for Booth Multipliers, IEEE Design & Test, v.15 n.3, p.105-111, July 1998 [doi>10.1109/54.706041]
	12	A. Paschalis , D. Gizopoulos , N. Kranitis , M. Psarakis , Y. Zorian, An effective BIST architecture for fast multiplier cores, Proceedings of the conference on Design, automation and test in Europe, p.28-es, January 1999, Munich, Germany [doi>10.1145/307418.307469]
	13	Dimitris Gizopoulos , Antonis M. Paschalis , Yervant Zorian, An Effective BIST Scheme for Datapaths, Proceedings of the IEEE International Test Conference on Test and Design Validity, p.76-85, October 20-25, 1996
	14	John P. Hayes, Computer architecture and organization; (2nd ed.), McGraw-Hill, Inc., New York, NY, 1988

CITED BY 4

	Nektarios Kranitis , Antonis Paschalis , Dimitris Gizopoulos , Yervant Zorian, Instruction-Based Self-Testing of Processor Cores, Journal of Electronic Testing: Theory and Applications, v.19 n.2, p.103-112, April 2003
	Marcelo Moraes , Érika Cota , Luigi Carro , Flávio Wagner , Marcelo Lubaszewski, A constraint-based solution for on-line testing of processors embedded in real-time applications, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
	Chung-Ho Chen , Chih-Kai Wei , Tai-Hua Lu , Hsun-Wei Gao, Software-based self-testing with multiple-level abstractions for soft processor cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.5, p.505-517, May 2007
	Tai-Hua Lu , Chung-Ho Chen , Kuen-Jong Lee, A hybrid software-based self-testing methodology for embedded processor, Proceedings of the 2008 ACM symposium on Applied computing, March 16-20, 2008, Fortaleza, Ceara, Brazil