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On compiling algorithms for arithmetic expressions
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Communications of the ACM archive
Volume 10 ,  Issue 8  (August 1967) table of contents
Pages: 492 - 494  
Year of Publication: 1967
ISSN:0001-0782
Author
Ikuo Nakata  Central Research Laboratory, Hitachi, Ltd., Tokyo, Japan
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 28,   Citation Count: 24
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ABSTRACT

This paper deals with algorithms concerning arithmetic expressions used in a FORTRAN IV compiler for a HITAC-5020 computer having n accumulators. The algorithms generate an object code which minimizes the frequency of storing and recovering the partial results of the arithmetic expressions in cases where there are several accumulators.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
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MURATA, K., AND NAKAZAWA, K. Very high speed serial and serial-parallel computers HITAC 5020 and 5020E. Proc. AFIPS 1964 Fall Joint Comput. Conf., Vol. 26, Pt. 1. 187-203.
 
3
FERGUSON, DAVID E. LARC scientific compiler phase 7 internal system manual. UNIVAC Div. of Sperry Rand Corp., 1961.

CITED BY  24