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ABSTRACT
A technique for simulating the detailed logic networks of large and active digital systems is described. Essential objectives sought are improved ease and economy in model generation, economy in execution time and space, and a facility for handling simultaneous activities. The main results obtained are a clear and useful separation of structural and behavioral model description, a reduction of manual tasks in converting Boolean logic into a structural model, the elimination of manual processes in achieving exclusive simulation of activity, an event-scheduling technique which does not deteriorate in economy as the event queue grows in length, and a simulation procedure which deals effectively with any mixture of serial and simultaneous activities. The passage of time is simulated in a precise, quantitative fashion, and systems to be simulated may be combinations of synchronous and asynchronous logic. Certain aspects of the techniques described may be used for the simulation of network structures other than digital networks.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CASE, P. W., GRAFF, H. M., GRIFFITH, L. E., LECLERCQ, A. R., MURLEY, W. B., AND SPENCE, W.M. Solid logic design automation. IBM J . (Apr. 1964), 127-140.
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WILLIAMS, L .R . SLAM II, digital network simulation program developed at TRW Systems. {Operational since 1967}
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HARMER, D. L., AND LACY, D .L . SIMSTRAN, digital network simulation program under development at Data Systems Division, Autonetics, North American Rockwell Corp., 1968.
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CITED BY 38
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E. Ulrich , D. Lacy , N. Phillips , J. Tellier , M. Kearney , T. Elkind , R. Beaven, High-speed concurrent fault simulation with vectors and scalars, Proceedings of the 17th conference on Design automation, p.374-380, June 23-25, 1980, Minneapolis, Minnesota, United States
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Mario Tokoro , Masayuki Sato , Masayuki Ishigami , Eiji Tamura , Terunobu Ishimitsu , Hisashi Ohara, A module level simulation technique for systems composed of LSI's and MSI's, Proceedings of the 15th conference on Design automation, p.418-427, June 19-21, 1978, Las Vegas, Nevada, United States
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V. D. Agrawal , A. K. Bose , P. Kozak , H. N. Nham , E. Pacas-Skewes, A mixed-mode simulator, Proceedings of the 17th conference on Design automation, p.618-625, June 23-25, 1980, Minneapolis, Minnesota, United States
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H. B. Rigas , H. B. Jacoby , V. B. Hunt, An interactive logic activity modelling program, Proceedings of the ACM annual conference, p.867-876, August 01-01, 1972, Boston, Massachusetts, United States
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Tsuyoshi Takahashi , Satoshi Kojima , Osamu Yamashiro , Kazuhiko Eguchi , Hideki Fukuda, An MOS digital network model on a modified thevenin equivalent for logic simulation, Proceedings of the 21st conference on Design automation, p.549-555, June 25-27, 1984, Albuquerque, New Mexico, United States
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Yasuhiro Ohno , Masayuki Miyoshi , Katsuya Sato, Logic verification system for very large computers using LSI's, Proceedings of the 16th Conference on Design automation, p.367-374, June 25-27, 1979, San Diego, CA, United States
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INDEX TERMS
Primary Classification:
C.
Computer Systems Organization
Additional Classification:
I.
Computing Methodologies
I.6
SIMULATION AND MODELING
General Terms:
Design,
Performance,
Theory
Keywords:
digital simulation,
large systems simulation,
logical simulation,
network structures,
parallel events,
queueing,
scheduling,
simulation,
simultaneous activities
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