An FPGA-based video compressor for H.263 compatible bit streams

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An FPGA-based video compressor for H.263 compatible bit streams

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 207 - 212

Year of Publication: 2001

ISBN:1-58113-341-3

Authors

G. Lienhart	Dept. for Computer Science V, University of Mannheim, B6-26, D-68131 Mannheim, Germany
R. Männer	Dept. for Computer Science V, University of Mannheim, B6-26, D-68131 Mannheim, Germany
K. H. Noffz	Silicon Software GmbH, M2-16, D-68161 Mannheim, Germany
R. Lay	Silicon Software GmbH, M2-16, D-68161 Mannheim, Germany

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 6, Downloads (12 Months): 33, Citation Count: 0

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ABSTRACT

This paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf FPGA1 and is embedded in a PCI plug-in card2 with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, was implemented. The strategies, which have been applied to build the complex encoding operations, are treated in this paper. The complete application is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day FPGAs. The use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs.

REFERENCES

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