A pipelined architecture for partitioned DWT based lossy image compression using FPGA's

ABSTRACT

Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression \cite{TenLectures, Shapiro, Spiht}. However, the algorithms proposed in literature assume random access to the whole image. This makes the algorithms unsuitable for hardware solutions because of extensive access to external memory. Here, we present an efficient architecture for computing DWT of images, which is based on a partitioned approach for lossy image compression~\cite{Ritter}. The architecture achieves its computational power by using pipelining and taking advantage of the flexible memory configurations available in FPGA's.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware

Additional Classification:
  B. Hardware
  B.2 ARITHMETIC AND LOGIC STRUCTURES
      B.2.1 Design Styles
          Subjects: Pipeline
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware

  I. Computing Methodologies
  I.4 IMAGE PROCESSING AND COMPUTER VISION
      I.4.2 Compression (Coding)
          Subjects: Approximate methods

General Terms:
Algorithms, Design, Performance

Keywords:
FPGA, Xilinx, architecture, embedded zero tree coding, field programmable gate arrays, lossy image compression, pipelining, wavelet transformation