Run-Time defect tolerance using JBits

ABSTRACT

The ability to tolerate defects in semiconductor devices has the potential for both increasing yields of devices being manufactured and making it economically feasible to manufacture even larger devices. While FPGA devices appear to be well suited to providing defect tolerance, practical application of existing research and techniques has been somewhat elusive. One barrier to acceptance is that existing defect tolerance techniques for FPGAs have tended to rely on either modifications to device architectures or modifications to design tools. We describe a software-based technique for providing defect tolerance which requires neither changes to device hardware or software tools. This approach uses the Xilinx JBits$^{(tm)}$ toolkit and operates at the core library level. Addressing defect tolerance locally using core library elements rather than taking a global approach helps provide direct support for run-time reconfiguration. Circuits may be configured and reconfigured rapidly in the presence of these defects. This rapid configuration also provides a path for practical use in more traditional manufacturing environments.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Experimentation, Performance

Keywords:
FPGA, Java, cores, defect tolerance, run-time reconfiguration