A memory coherence technique for online transient error recovery of FPGA configurations

ABSTRACT

The partial reconfiguration feature of some of the current-generation Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in on-chip configuration data. Such an error recovery process can be executed online with minimal interference of user applications. However, because Look-up Tables (LUTs) in Configurable Logic Blocks (CLBs) of FPGAs can also implement memory modules for user applications, a memory coherence issue arises such that memory contents in user applications may be altered by the online configuration data recovery process. In this paper, we investigate this memory coherence problem and propose a memory coherence technique that does not impose extra constraints on the placement of memory-configured LUTs. Theoretical analyses and simulation results show that the proposed technique guarantees the memory coherence with a very small (on the order of 0.1%) execution time overhead in user applications.

REFERENCES

• 1: Altera Inc., http://www.altera.com, 2000.
• 2: James Archibald , Jean-Loup Baer, Cache coherence protocols: evaluation using a multiprocessor simulation model, ACM Transactions on Computer Systems (TOCS), v.4 n.4, p.273-298, Nov. 1986 [doi>10.1145/6513.6514]
• 3: Carmichael, C., E. Fuller, P. Blain, and M. Caffrey, SEU Mitigation Techniques for Virtex FPGAs in Space applications, MAPLD '99, Sept. 1999.
• 4: Douglas Chang , Malgorzata Marek-Sadowska, Partitioning sequential circuits on dynamically reconfiguable FPGAs, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.161-167, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275136]
• 5: Debaleena Das , Nur A. Touba, A Low Cost Approach for Detecting, Locating, and Avoiding Interconnect Faults in FPGA-Based Reconfigurable Systems, Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', p.266, January 10-13, 1999
• 6: Emmert, J. M., and D. Bhatia, Incremental Routing in FPGAs, Proc. of 11 th Annual IEEE International ASIC Conference, pp. 217-221, 1998.
• 7: Fran Hanchek , Shantanu Dutt, Methodologies for Tolerating Cell and Interconnect Faults in FPGAs, IEEE Transactions on Computers, v.47 n.1, p.15-33, January 1998 [doi>10.1109/12.656073]
• 8: Wei-Je Huang , Nirmal Saxena , Edward J. McCluskey, A Reliable LZ Data Compressor on Reconfigurable Coprocessors, Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, p.249, April 17-19, 2000
• 9: Wei-Je Huang , E. J. McCluskey, Transient errors and rollback recovery in LZ compression, Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing, p.128, December 18-20, 2000
• 10: Kelem, S., XAPP151: Virtex Configuration Architecture Advanced Users' Guide, Xilinx Application Note, http://www.xilinx.com, 2000.
• 11: John Lach , William H. Mangione-Smith , Miodrag Potkonjak, Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures, Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems, p.386-394, November 01-03, 1999
• 12: Vijay Lakamraju , Russell Tessier, Tolerating operational faults in cluster-based FPGAs, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.187-194, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329205]
• 13: Nihar R. Mahapatra , Shantanu Dutt, Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs, Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, p.122, June 15-18, 1999
• 14: Mitra, S., P. P. Shirvani, and E.J. McCluskey, Fault Location in FPGA-Based Reconfigurable Systems, IEEE Intl. High Level Design Validation and Test Workshop, 1998.
• 15: Subhasish Mitra , Edward J. McCluskey, WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?, Proceedings of the 2000 IEEE International Test Conference, p.985, October 03-05, 2000
• 16: Mark S. Papamarcos , Janak H. Patel, A low-overhead coherence solution for multiprocessors with private cache memories, Proceedings of the 11th annual international symposium on Computer architecture, p.348-354, January 1984
• 17: Dhiraj K. Pradhan, Fault-tolerant computer system design, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
• 18: Saxena, N. R., and E. J. McCluskey, Dependable Adaptive Computing Systems, IEEE Systems, Man, and Cybernetics Conf., pp. 2172-2177, Oct. 11-14, 1998.
• 19: Nirmal R. Saxena , Santiago Fernandez-Gomez , Wei-Je Huang , Subhasish Mitra , Shu-Yi Yu , Edward J. McCluskey, Dependable Computing and Online Testing in Adaptive and Configurable Systems, IEEE Design & Test, v.17 n.1, p.29-41, January 2000 [doi>10.1109/54.825675]
• 20: Steve Trimberger, Scheduling designs into a time-multiplexed FPGA, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.153-160, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275135]
• 21: Xilinx Inc., http://www.xilinx.com, 2000.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays

General Terms:
Design, Management, Performance

Keywords:
FPGA, error recovery, fault tolerance, memory coherence