The effect of reconfigurable units in superscalar processors

ABSTRACT

This paper describes OneChip, a third generation reconfigurable processor architecture that integrates a Reconfigurable Functional Unit (RFU) into a superscalar Reduced Instruction Set Computer (RISC) processor's pipeline. The architecture allows dynamic scheduling and dynamic reconfiguration. It also provides support for pre-loading configurations and for Least Recently Used (LRU) configuration management.To evaluate the performance of the OneChip architecture, several off-the-shelf software applications were compiled and executed on Sim-OneChip, an architecture simulator for OneChip that includes a software environment for programming the system. The architecture is compared to a similar one but without dynamic scheduling and without an RFU. OneChip achieves a performance improvement and shows a speedup range from 2.16 up to 32 for the different applications and data sizes used. The results show that dynamic scheduling helps performance the most on average, and that the RFU will always improve performance the best when most of the execution is in the RFU.

REFERENCES

• 1: D.Burger and T.M.Austin.The SimpleScalar tool set,version 2.0.Tech ical Report 1342,U iversity of Wisco sin-Madison,Computer Sciences Departme t, 1997.
• 2: Timothy J. Callahan , John R. Hauser , John Wawrzynek, The Garp Architecture and C Compiler, Computer, v.33 n.4, p.62-69, April 2000 [doi>10.1109/2.839323]
• 3: J.E.Carrillo Esparza.Evaluation of the O eChip reconfigurable processor.Master 's thesis,University of Toronto,2000.
• 4: A.DeHon.DPGA-coupled microprocessors: Commodity ICs for the early 21st century.I Proceedings IEEE Workshop on Fiel d-Programmabl e Custom Computing Machines pages 31 -39,Apr.1994.
• 5: Seth Copen Goldstein , Herman Schmit , Mihai Budiu , Srihari Cadambi , Matt Moe , R. Reed Taylor, PipeRench: A Reconfigurable Architecture and Compiler, Computer, v.33 n.4, p.70-77, April 2000 [doi>10.1109/2.839324]
• 6: Scott Hauck, Configuration prefetch for single context reconfigurable coprocessors, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.65-74, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275121]
• 7: S. Hauck , T. W. Fry , M. M. Hosler , J. P. Kao, The Chimaera reconfigurable functional unit, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.87, April 16-18, 1997
• 8: Scott Hauck , Zhiyuan Li , Eric Schwabe, Configuration Compression for the Xilinx XC6200 FPGA, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.138, April 15-17, 1998
• 9: John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
• 10: J.A.Jacob.Memory interfacing for the O eChip recon .gurable processor.Master 's thesis,University of Toronto,1998.
• 11: Jeffrey A. Jacob , Paul Chow, Memory interfacing and instruction specification for reconfigurable processors, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.145-154, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296446]
• 12: Dannie Lau , Aaron Schneider , Milos D. Ercegovac , John Villasenor, FPGA-Based Structures for On-Line FFT and DCT, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.310, April 21-23, 1999
• 13: Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
• 14: Guangming Lu , Hartej Singh , Ming-Hau Lee , Nader Bagherzadeh , Fadi J. Kurdahi , Eliseu M. Chaves Filho, The MorphoSys Parallel Reconfigurable System, Proceedings of the 5th International Euro-Par Conference on Parallel Processing, p.727-734, August 31-September 03, 1999
• 15: MIPS Tech ologies,I corporated.MIPS R10000 (T5) Superscalar Microprocessor, technical brief Oct.1994.
• 16: Takashi Miyamori , Kunle Olukotun, A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.2, April 15-17, 1998
• 17: V.S.Pai,P.Ranganathan,and S.V.Adve.RSIM:A execution-drive simulator for ILP-based shared-memory multiprocessors a d uniprocessors.In Proceedings of the Third Workshop on Computer Architecture Education Feb.1997.
• 18: Rahul Razdan , Michael D. Smith, A high-performance microarchitecture with hardware-programmable functional units, Proceedings of the 27th annual international symposium on Microarchitecture, p.172-180, November 30-December 02, 1994, San Jose, California, United States [doi>10.1145/192724.192749]
• 19: C. R. Rupp , M. Landguth , T. Garverick , E. Gomersall , H. Holt , J. M. Arnold , M. Gokhale, The NAPA Adaptive Processing Architecture, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.28, April 15-17, 1998
• 20: A.Silberschatz and P.B.Galvin.Operating System Addiso Wesley Lo gma ,Inc.,USA,.fth edition edition,1998.
• 21: Xinan Tang , Manning Aalsma , Raymond Jou, A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors, Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications, p.29-38, August 27-30, 2000
• 22: R.D.Wittig and P.Chow.OneChip:An FPGA processor with recon .gurable logic.In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines pages 126 -135,Mar.1996.
• 23: Zhi Alex Ye , Andreas Moshovos , Scott Hauck , Prithviraj Banerjee, CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit, Proceedings of the 27th annual international symposium on Computer architecture, p.225-235, June 2000, Vancouver, British Columbia, Canada

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

General Terms:
Experimentation, Management, Performance

Keywords:
OneChip, reconfigurable processors, superscalar processors