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Evaluation of the streams-C C-to-FPGA compiler: an applications perspective
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Source International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays table of contents
Monterey, California, United States
Pages: 134 - 140  
Year of Publication: 2001
ISBN:1-58113-341-3
Authors
Jan Frigo  Los Alamos National Laboratory, Los Alamos, NM
Maya Gokhale  Los Alamos National Laboratory, Los Alamos, NM
Dominique Lavenier  IRISA - CNRS, Campus de Beaulieu, 35042 Rennes cedex, France
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 3,   Downloads (12 Months): 55,   Citation Count: 23
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ABSTRACT

The Streams-C compiler ([5]) synthesizes hardware circuits for reconfigurable FPGA-based computers from parallel C programs. The Streams-C language consists of a small number of libraries and intrinsic functions added to a synthesizable subset of C, and supports a communicating process programming model. The processes may be either software or hardware processes, and the compiler manages communication among the processes transparently to the programmer. For the hardware processes, the compiler generates Register-Transfer-Level (RTL) VHDL, targeting multiple FPGAs with dedicated memories. For the software processes, a multi-threaded software program is generated.The Streams-C language and compiler offer a very high level of expressivity for reconfigurable computing application development, particularly for stream-processing applications. We find this is reflected in productivity, for a factor of up to 10 times improvement in time to produce a program. However, use of the tool in the ``real world'' is predicated on performance: only if such a compiler can deliver performance comparable to hand-coded performance will it be used in practice.This paper presents an application study of the Streams-C compiler. Four applications have been written in Streams-C and compiled to the AMC Wildforce board containing Xilinx 4036's. Those same applications have been hand-coded in a combination of RTL and structural VHDL. We compare performance of the generated code with the hand-optimized code. Our study shows that the compiler-generated designs are 1.37--4 times the area and $1/2$--1 times the clock frequency of the hand designs. We find that the compiler, based on the SUIF infrastructure, can be greatly improved through various standard compiler optimizations that are not currently being exploited. Thus we are currently re-writing a public domain version of Streams-C to better optimize and target the Virtex chip.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Joseph Arrowood. Comparison of filter banks for signal detection. In LAUR Number 99-4551, Los Alamos, NM, March 2000.
 
2
Xilinx Corp. http://www.xilinx.com/xilinxonline/jbits.htm. 1999.
 
3
M. B. Gokhale, J. Frigo, and J. Stone. Parallel c programming of reconfigurable computers: the Streams-C approach. In HPEC 2000, September 2000.
 
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Mary Hall et al. Defacto: A design environment for adaptive computing technology. Proceedings of the 6th Recongurable Architectures Workshop (RAW'99), 1999.
 
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Dominique Lavenier, James Theiler, John Szymanski, Maya Gokhale, and Janette Frigo. Fpga implementation of the pixel purity index algorithm. In SPIE, FPGAs and Reconfigurable Processors for Computing and Applications, vol 4212, Boston, MA, November 2000.
 
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Miriam Leeser. Applying reconfigurable hardware to segmentation for multispectral imagery. InHPEC 2000, Boston, MA, September 2000.
 
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S. Periyayacheri et al. Library functions in reconfigurable hardware for matrix and signal processing operations in matlab. Proc. 11th IASTED Parallel and Distributed Computing and Systems Conference (PDCS'99), November 1999.
 
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CITED BY  23

Collaborative Colleagues:
Jan Frigo: colleagues
Maya Gokhale: colleagues
Dominique Lavenier: colleagues