Interconnect pipelining in a throughput-intensive FPGA architecture

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Interconnect pipelining in a throughput-intensive FPGA architecture

Full text

Pdf (204 KB)

Source

International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 153 - 160

Year of Publication: 2001

ISBN:1-58113-341-3

Authors

Amit Singh
Arindam Mukherjee
Malgorzata Marek-Sadowska

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 37, Citation Count: 10

Additional Information:

abstract references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/360276.360323 What is a DOI?

ABSTRACT

Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, cirðcuits inherently utilize latches. Inside the synthesized structures they are used for signal skewing, and on the interconnects to guarðantee the correct arrival times at the inputs. Recently, we proposed a novel high-throughput FPGA architecture based on the wave-steering design principle to handle throughput-intensive applicaðtions. Previously our work was focussed mainly on the Logic Block (LB) design. In this paper we discuss a pipelined interconðnect scheme to support the strict timing requirements that is necesðsitated by the wave-steered design style. We characterize designs that best fit the new architecture and show that as technology scales down towards deep submicron (DSM), this FPGA fabric shows an increasing throughput performance.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	V. Bertacco, "Decision Diagrams and Pass Transistor Logic Synthesis", Proc. of the ACM/IEEE International Workshop on Logic Synthesis, May 1997, pp. 1-5.
	2	Vaughn Betz , Jonathan Rose , Alexander Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Norwell, MA, 1999
	3	Vaughn Betz , Jonathan Rose, VPR: A new packing, placement and routing tool for FPGA research, Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, p.213-222, September 01-03, 1997
	4	Eduardo I. Boemo , Sergio López-Buedo , Juan M. Meneses, Some experiments about wave pipelining on FPGA's, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.2, p.232-237, June 1998 [doi>10.1109/92.678876]
	5	Gaetano Borriello , Carl Ebeling , Scott A. Hauck , Steven Burns, The triptych FPGA architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.4, p.491-501, Dec. 1995 [doi>10.1109/92.475968]
	6	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	7	P. Buch et al, On Synthesizing Pass Transistor Networks, Proc. of the ACM/IEEE International Workshop on Logic Synthesis, May 1997, pp. 1-8.
	8	Premal Buch , Amit Narayan , A. Richard Newton , A. Sangiovanni-Vincentelli, Logic synthesis for large pass transistor circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.663-670, November 09-13, 1997, San Jose, California, United States
	9	W.P. Burleson, M. Ciesielski, F. Klass, W. Liu, Wave-Pipelining: A Tutorial and Research Survey IEEE Transactions on VLSI Systems, Vol.6, No.3, Sep.'98, pp. 464-470.
	10	T. Chappell, A 2-ns cycle, 3.8ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture, IEEE Journal of Solid-State Circuits, vol 26 (no.11), Nov 1991, pp.1577-85.
	11	J. Cong, Y. Ding, FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs, IEEE Transactions on Computer- Aided Design (CAD), 13(1):1-12, January 1994, pp. 1-12.
	12	M. Feuer, Connectivity of Random Logic, IEEE Transactions on Computers, vol. C-J31, no.1, January 1982, pp.29- 33.
	13	S. Y. Kung, VLSI array processors, Prentice-Hall, Inc., Upper Saddle River, NJ, 1987
	14	W.K.C. Lam, R.K.Brayton and A.L.Sangiovanni-Vincentelli, Valid Clock Frequencies and Their Computation in Wave Pipelined Circuits IEEE Transactions on CAD of IC and Systems, Vol. 15, No.7, July 1996, pp. 791-807.
	15	Arindam Mukherjee , Ranganathan Sudhakar , Malgorzata Marek-Sadowska , Stephen I. Long, Wave steering in YADDs: a novel non-iterative synthesis and layout technique, Proceedings of the 36th ACM/IEEE conference on Design automation, p.466-471, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309981]
	16	A. Mukherjee, M. Marek-Sadowska, S.I. Long,Wave Pipelining YADDs- A Feasibility Study, Proc. IEEE Custom Integrated Circuits Conference, May 1999, pp 559-562.
	17	U. Peisl, Image Correlation using a bit level systolic array, IEEE International Symposium on Circuits and Systems, June 1988, pp. 2689-2693.
	18	R. Ray, A Placement and Routing Algorithm for a new High Throughput FPGA, MS Thesis, UCSB 1999.
	19	Amit Singh , Luca Macchiarulo , Arindam Mukherjee , Malgorzata Marek-Sadowska, A novel high throughput reconfigurable FPGA architecture, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.22-29, February 10-11, 2000, Monterey, California, United States [doi>10.1145/329166.329174]
	20	R. Sudhakar, YADDA: Layout Synthesis using Pass Transistor Logic, MS Thesis, UCSB, 1998.
	21	K. Taki, A Survey for Pass-Transistor Logic Technologies, Proc. Asia South-Pacific Design Automation Conference, February 1998, pp. 223-226.
	22	William Tsu , Kip Macy , Atul Joshi , Randy Huang , Norman Walker , Tony Tung , Omid Rowhani , Varghese George , John Wawrzynek , André DeHon, HSRA: high-speed, hierarchical synchronous reconfigurable array, Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays, p.125-134, February 21-23, 1999, Monterey, California, United States [doi>10.1145/296399.296442]
	23	Brian Von Herzen, Signal processing at 250 MHz using high-performance FPGA's, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.2, p.238-246, June 1998 [doi>10.1109/92.678878]
	24	Luca Macchiarulo , Shih-Ming Shu , Malgorzata Marek-Sadowska, Wave steered FSMs, Proceedings of the conference on Design, automation and test in Europe, p.270-276, March 27-30, 2000, Paris, France [doi>10.1145/343647.343779]
	25	Luca Macchiarulo , Malgorzata Marek-Sadowska, Wave-steering one-hot encoded FSMs, Proceedings of the 37th conference on Design automation, p.357-360, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337440]
	26	The Programmable Logic Data Book, Xilinx Inc. 1999.
	27	URL: http://www.xilinx.com/products/logicore/lcoredes.htm

CITED BY 10

	Akshay Sharma , Carl Ebeling , Scott Hauck, PipeRoute: a pipelining-aware router for FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Amit Singh , Arindam Mukherjee , Luca Macchiarulo , Malgorzata Marek-Sadowska, PITIA: an FPGA for throughput-intensive applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.3, p.354-363, June 2003
	Amit Singh , Arindam Mukherjee , Malgorzata Marek-Sadowska, Latency and latch count minimization in wave steered circuits, Proceedings of the 38th conference on Design automation, p.383-388, June 2001, Las Vegas, Nevada, United States
	Akshay Sharma , Katherine Compton , Carl Ebeling , Scott Hauck, Exploration of pipelined FPGA interconnect structures, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	Amit Singh , Malgorzata Marek-Sadowska, FPGA interconnect planning, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA
	John Teifel , Rajit Manohar, Highly pipelined asynchronous FPGAs, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	John Teifel , Rajit Manohar, An Asynchronous Dataflow FPGA Architecture, IEEE Transactions on Computers, v.53 n.11, p.1376-1392, November 2004
	Neal K. Bambha , Shuvra S. Bhattacharyya, Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.99-112, February 2005
	Richard B. Kujoth , Chi-Wei Wang , Jeffrey J. Cook , Derek B. Gottlieb , Nicholas P. Carter, A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor, Microprocessors & Microsystems, v.31 n.2, p.146-159, March, 2007
	Paul Teehan , Guy G.F. Lemieux , Mark R. Greenstreet, Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs, Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays, February 22-24, 2009, Monterey, California, USA