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Reprogrammable network packet processing on the field programmable port extender (FPX)
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Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays table of contents
Monterey, California, United States
Pages: 87 - 93  
Year of Publication: 2001
ISBN:1-58113-341-3
Authors
John W. Lockwood  Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
Naji Naufel  Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
Jon S. Turner  Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
David E. Taylor  Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 33,   Citation Count: 16
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ABSTRACT

A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two Field Programmable Gate Arrays (FPGAs). Packet processing functions in the system are implemented as dynamically-loadable modules.Core functionality of the FPX is implemented on an FPGA called the Networking Interface Device (NID). The NID contains the logic to transmit and receive packets over a network, dynamically reprogram hardware modules, and route individual traffic flows. A full, non-blocking, switch is implemented on the NID to route packets between the networking interfaces and the modular components. Modular components of the FPX are implemented on a second FPGA called the Reprogrammable Application Device (RAD). Modules are loaded onto the RAD via reconfiguration and/or partial partial reconfiguration of the FPGA.Through the combination of the NID and the RAD, the FPX can individually reconfigure the packet processing functionality for one set of traffic flows, while the rest of the system continues to operate. The platform simplifies the development and deployment of new hardware-accelerated packet processing circuits. The modular nature of the system allows an active router to migrate functionality from softare plugins to hardware modules.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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CITED BY  16

Collaborative Colleagues:
John W. Lockwood: colleagues
Naji Naufel: colleagues
Jon S. Turner: colleagues
David E. Taylor: colleagues