| Reprogrammable network packet processing on the field programmable port extender (FPX) |
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International Symposium on Field Programmable Gate Arrays
archive
Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
table of contents
Monterey, California, United States
Pages: 87 - 93
Year of Publication: 2001
ISBN:1-58113-341-3
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Authors
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John W. Lockwood
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Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
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Naji Naufel
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Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
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Jon S. Turner
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Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
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David E. Taylor
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Department of Computer Science, Applied Research Lab, Washington University, 1 Brookings Drive, Saint Louis, MO
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Downloads (6 Weeks): 5, Downloads (12 Months): 33, Citation Count: 16
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ABSTRACT
A prototype platform has been developed that allows processing of packets at the edge of a multi-gigabit-per-second network switch. This system, the Field Programmable Port Extender (FPX), enables packet processing functions to be implemented as modular components in reprogrammable hardware. All logic on the on the FPX is implemented in two Field Programmable Gate Arrays (FPGAs). Packet processing functions in the system are implemented as dynamically-loadable modules.Core functionality of the FPX is implemented on an FPGA called the Networking Interface Device (NID). The NID contains the logic to transmit and receive packets over a network, dynamically reprogram hardware modules, and route individual traffic flows. A full, non-blocking, switch is implemented on the NID to route packets between the networking interfaces and the modular components. Modular components of the FPX are implemented on a second FPGA called the Reprogrammable Application Device (RAD). Modules are loaded onto the RAD via reconfiguration and/or partial partial reconfiguration of the FPGA.Through the combination of the NID and the RAD, the FPX can individually reconfigure the packet processing functionality for one set of traffic flows, while the rest of the system continues to operate. The platform simplifies the development and deployment of new hardware-accelerated packet processing circuits. The modular nature of the system allows an active router to migrate functionality from softare plugins to hardware modules.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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John W. Lockwood , Jon S. Turner , David E. Taylor, Field programmable port extender (FPX) for distributed routing and queuing, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.137-144, February 10-11, 2000, Monterey, California, United States
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J. Lockwood and D.Lim, Hello World:A imple application for the field programmable port extender (FPX), tech. rep., WUCS-00-12, Washington University, Department of Computer Science, July 11, 2000.
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Field Programmable Port Extender Homepage. http://www.arl.wustl.edu/projects/fpx/Aug. 2000.
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S. Choi, J. Dehart, R. Keller, J. Lockwood, J. Turner, and T. Wolf, Design of a flexible open platform for high performance active networks, in Allerton Conference (Champaign,IL), 1999.
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CITED BY 16
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Edson L. Horta , John W. Lockwood , David E. Taylor , David Parlour, Dynamic hardware plugins in an FPGA with partial run-time reconfiguration, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
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Domingos S. S. Carneiro , Paulo V. A. Pinheiro , Pedro H. Prudêncio , Daniel N. S. Cavalcante , Diego V. S. Sousa , Rudy M. Braquehais , Thially V. P. Marrocos , Marcial P. Fernandez, IP-checksum incremental update method proposal for efficient use of energy in wireless environments, Proceedings of the 2007 Euro American conference on Telematics and information systems, May 14-17, 2007, Faro, Portugal
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Jad Naous , David Erickson , G. Adam Covington , Guido Appenzeller , Nick McKeown, Implementing an OpenFlow switch on the NetFPGA platform, Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems, November 06-07, 2008, San Jose, California
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INDEX TERMS
Primary Classification:
C.
Computer Systems Organization
C.2
COMPUTER-COMMUNICATION NETWORKS
C.2.1
Network Architecture and Design
Subjects:
Packet-switching networks
Additional Classification:
B.
Hardware
B.4
INPUT/OUTPUT AND DATA COMMUNICATIONS
B.7
INTEGRATED CIRCUITS
General Terms:
Design,
Experimentation,
Theory
Keywords:
ATM,
FPGA,
IP,
Internet,
hardware,
modularity,
network,
packet,
processing,
reconfiguration,
routing
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