Performance improvement with circuit-level speculation

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Performance improvement with circuit-level speculation

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 348 - 355

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Tong Liu	Intel Corporation
Shih-Lien Lu	Intel Corporation

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 28, Citation Count: 6

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 6

	Gabriel H. Loh, Exploiting data-width locality to increase superscalar execution bandwidth, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Toshinori Sato , Itsujiro Arita, Constructive timing violation for improving energy efficiency, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
	Shih-Lien Lu, Speeding Up Processing with Approximation Circuits, Computer, v.37 n.3, p.67-73, March 2004
	Hai Li , Yiran Chen , Kaushik Roy , Cheng-Kok Koh, SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Dan Ernst , Nam Sung Kim , Shidhartha Das , Sanjay Pant , Rajeev Rao , Toan Pham , Conrad Ziesler , David Blaauw , Todd Austin , Krisztian Flautner , Trevor Mudge, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.7, December 03-05, 2003
	Smruti Sarangi , Brian Greskamp , Abhishek Tiwari , Josep Torrellas, EVAL: Utilizing processors with variation-induced timing errors, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.423-434, November 08-12, 2008