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Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors
Full text Publisher SitePublisher Site ,  PdfPdf (874 KB),  PsPs (44.21 MB)
Source International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents
Monterey, California, United States
Pages: 337 - 347  
Year of Publication: 2000
ISBN:1-58113-196-8
Authors
Amirali Baniasadi  Electrical and Computer Engineering, Northwestern University
Andreas Moshovos  Electrical And Computer Engineering, University of Toronto
Sponsors
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 21,   Citation Count: 20
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Haitham Akkary , Michael A. Driscoll, A dynamic multithreading processor, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.226-236, November 1998, Dallas, Texas, United States
 
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D. Burger and T. M. Austin. The Simple Scalar tool set, version 2.0. Technical Report Computer Sciences Tech. Report #1342, University of Wisconsin-Madison, June 1997.
 
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R. Canal, J. M. Parcerisa, and A. Gonzalez. Dynamic Cluster Assignment Mechanisms. In Proc. High Performance Architecture 6, Jan. 2000.
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George Z. Chrysos , Joel S. Emer, Memory dependence prediction using store sets, Proceedings of the 25th annual international symposium on Computer architecture, p.142-153, June 27-July 02, 1998, Barcelona, Spain
 
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Keith I. Farkas , Paul Chow , Norman P. Jouppi , Zvonko Vranesic, The multicluster architecture: reducing cycle time through partitioning, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.149-159, December 01-03, 1997, Research Triangle Park, North Carolina, United States
7
Lance Hammond , Mark Willey , Kunle Olukotun, Data speculation support for a chip multiprocessor, Proceedings of the eighth international conference on Architectural support for programming languages and operating systems, p.58-69, October 02-07, 1998, San Jose, California, United States
8
Toni Juan , Sanji Sanjeevan , Juan J. Navarro, Dynamic history-length fitting: a third level of adaptivity for branch prediction, Proceedings of the 25th annual international symposium on Computer architecture, p.155-166, June 27-July 02, 1998, Barcelona, Spain
 
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E. J. McLellan , D. A. Webb, The Alpha 21264 Microprocessor Architecture, Proceedings of the International Conference on Computer Design, p.90, October 05-05, 1998
 
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Doug Matzke, Will Physical Scalability Sabotage Performance Gains?, Computer, v.30 n.9, p.37-39, September 1997  [doi>10.1109/2.612245]
11
Andreas Moshovos , Scott E. Breach , T. N. Vijaykumar , Gurindar S. Sohi, Dynamic speculation and synchronization of data dependences, Proceedings of the 24th annual international symposium on Computer architecture, p.181-193, June 01-04, 1997, Denver, Colorado, United States
12
Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
 
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Eric Rotenberg , Quinn Jacobson , Yiannakis Sazeides , Jim Smith, Trace processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.138-148, December 01-03, 1997, Research Triangle Park, North Carolina, United States
14
Gurindar S. Sohi , Scott E. Breach , T. N. Vijaykumar, Multiscalar processors, Proceedings of the 22nd annual international symposium on Computer architecture, p.414-425, June 22-24, 1995, S. Margherita Ligure, Italy
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G. S. Sohi , S. Vajapeyam, Instruction issue logic for high-performance, interruptable pipelined processors, Proceedings of the 14th annual international symposium on Computer architecture, p.27-34, June 02-05, 1987, Pittsburgh, Pennsylvania, United States  [doi>10.1145/30350.30354]
 
16
J. Steffan , T Mowry, The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization, Proceedings of the 4th International Symposium on High-Performance Computer Architecture, p.2, January 31-February 04, 1998

CITED BY  20
Gabriel H. Loh, Exploiting data-width locality to increase superscalar execution bandwidth, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
Brian Fields , Shai Rubin , Rastislav Bodík, Focusing processor policies via critical-path prediction, ACM SIGARCH Computer Architecture News, v.29 n.2, p.74-85, May 2001
Amirali Baniasadi, Balancing clustering-induced stalls to improve performance in clustered processors, Proceedings of the 2nd conference on Computing frontiers, May 04-06, 2005, Ischia, Italy
Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi, Dynamically managing the communication-parallelism trade-off in future clustered processors, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
Fernando Latorre , José González , Antonio González, Back-end assignment schemes for clustered multithreaded processors, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
Joan-Manuel Parcerisa , Julio Sahuquillo , Antonio Gonzalez , Jose Duato, On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.130-144, February 2005
Teresa Monreal , Victor Vinals , Jose Gonzalez , Antonio Gonzalez , Mateo Valero, Late Allocation and Early Release of Physical Registers, IEEE Transactions on Computers, v.53 n.10, p.1244-1259, October 2004
José González , Fernando Latorre , Antonio González, Cache organizations for clustered microarchitectures, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.46-55, June 20-20, 2004, Munich, Germany
Rajeev Balasubramonian, Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
R. González , A. Cristal , M. Pericas , M. Valero , A. Veidenbaum, An asymmetric clustered processor based on value content, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts
Aneesh Aggarwal , Manoj Franklin, Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency, IEEE Transactions on Computers, v.54 n.12, p.1496-1507, December 2005
Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi, Reducing the complexity of the register file in dynamic superscalar processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
Aneesh Aggarwal , Manoj Franklin, Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.10, p.944-955, October 2005
Peter G. Sassone , D. Scott Wills, Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.7-17, December 04-08, 2004, Portland, Oregon
Engin Ipek , Meyrem Kirman , Nevin Kirman , Jose F. Martinez, Core fusion: accommodating software diversity in chip multiprocessors, ACM SIGARCH Computer Architecture News, v.35 n.2, May 2007
Olivier Rochecouste , Gilles Pokam , André Seznec, A case for a complexity-effective, width-partitioned microarchitecture, ACM Transactions on Architecture and Code Optimization (TACO), v.3 n.3, p.295-326, September 2006
Angshuman Parashar , Sudhanva Gurumurthi , Anand Sivasubramaniam, A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy, ACM SIGARCH Computer Architecture News, v.32 n.2, p.376, March 2004
Pierre Salverda , Craig Zilles, A Criticality Analysis of Clustering in Superscalar Processors, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.55-66, November 12-16, 2005, Barcelona, Spain
Fernando Latorre , Grigorios Magklis , José González , Pedro Chaparro , Antonio González, Building a large instruction window through ROB compression, Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, p.41-48, September 16-16, 2007, Brasov, Romania
Teresa Monreal , Víctor Vinals , Antonio Gonzalez , Mateo Valero, Hardware support for early register release, International Journal of High Performance Computing and Networking, v.3 n.2/3, p.83-94, November 2005

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)
  C.5 COMPUTER SYSTEM IMPLEMENTATION

  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE
      I.2.8 Problem Solving, Control Methods, and Search
          Subjects: Heuristic methods

  K. Computing Milieux
  K.6 MANAGEMENT OF COMPUTING AND INFORMATION SYSTEMS
      K.6.2 Installation Management
          Subjects: Benchmarks


General Terms:
Algorithms, Design, Measurement, Performance, Standardization, Theory

Collaborative Colleagues:
Amirali Baniasadi: colleagues
Andreas Moshovos: colleagues

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