Reducing wire delay penalty through value prediction

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Reducing wire delay penalty through value prediction

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 317 - 326

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Joan-Manuel Parcerisa	Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, c/. Jordi Girona, 1-3 Mòdul C6, 08034 Barcelona, Spain
Antonio González	Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, c/. Jordi Girona, 1-3 Mòdul C6, 08034 Barcelona, Spain

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 19, Citation Count: 7

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	4	Ramon Canal , Joan-Manuel Parcerisa , Antonio Gonzalez, A Cost-Effective Clustered Architecture, Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, p.160, October 12-16, 1999
	5	R.Canal, J-M.Parcerisa, A. Gonz~lez. Dynamic Cluster Assignment Mechanisms. In Proc. of the 6th. Int. Symp. on High-Performance Computer Architecture, pp.132-142, Jan. 2000.
	6	Keith I. Farkas , Paul Chow , Norman P. Jouppi , Zvonko Vranesic, The multicluster architecture: reducing cycle time through partitioning, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.149-159, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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CITED BY 7

	Joan-Manuel Parcerisa , Julio Sahuquillo , Antonio Gonzalez , Jose Duato, On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.130-144, February 2005
	Mladen Berekovic , Sören Moch , Peter Pirsch, A scalable, clustered SMT processor for digital signal processing, ACM SIGARCH Computer Architecture News, v.32 n.3, p.62-69, June 2004
	José González , Fernando Latorre , Antonio González, Cache organizations for clustered microarchitectures, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.46-55, June 20-20, 2004, Munich, Germany
	Rajeev Balasubramonian, Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
	Aneesh Aggarwal , Manoj Franklin, Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency, IEEE Transactions on Computers, v.54 n.12, p.1496-1507, December 2005
	Aneesh Aggarwal , Manoj Franklin, Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.10, p.944-955, October 2005
	Timothy Mark Pinkston , Jeonghee Shin, Trends toward on-chip networked microsystems, International Journal of High Performance Computing and Networking, v.3 n.1, p.3-18, September 2005