Reducing wire delay penalty through value prediction

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Reducing wire delay penalty through value prediction

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 317 - 326

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Joan-Manuel Parcerisa	Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, c/. Jordi Girona, 1-3 Mòdul C6, 08034 Barcelona, Spain
Antonio González	Dept. d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, c/. Jordi Girona, 1-3 Mòdul C6, 08034 Barcelona, Spain

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 18, Citation Count: 7

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Vikas Agarwal , M. S. Hrishikesh , Stephen W. Keckler , Doug Burger, Clock rate versus IPC: the end of the road for conventional microarchitectures, Proceedings of the 27th annual international symposium on Computer architecture, p.248-259, June 2000, Vancouver, British Columbia, Canada
	2	Bohr, Mark T. Interconnect Scaling - The Real Limiter to High Performance ULSI. in Proc. of the 1995 IEEE Int. Electron Devices Meeting, pp. 241-244, 1995.
	3	D. Burger, T.M. Austin, S. Bennett. Evaluating Future Microprocessors: The SimpleScalar Tool Set, Tech. Report CS-TR-96-1308, Univ.Wisconsin-Madison, 1996.
	4	Ramon Canal , Joan-Manuel Parcerisa , Antonio Gonzalez, A Cost-Effective Clustered Architecture, Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, p.160, October 12-16, 1999
	5	R.Canal, J-M.Parcerisa, A. Gonz~lez. Dynamic Cluster Assignment Mechanisms. In Proc. of the 6th. Int. Symp. on High-Performance Computer Architecture, pp.132-142, Jan. 2000.
	6	Keith I. Farkas , Paul Chow , Norman P. Jouppi , Zvonko Vranesic, The multicluster architecture: reducing cycle time through partitioning, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.149-159, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	7	K.I.Farkas. Memory-system Design Considerations for Dynamically-scheduled Microprocessors, Ph.D. thesis, Department of Electrical and Computer Engineering, Univ. of Toronto, Canada, January 1997.
	8	F.Gabbay and A.Mendelson. Speculative Execution Based on Value Prediction, TR. #1080, Technion, 1996.
	9	J.GonzAlez and A.Gonz~lez. Memory Address Prediction for Data Speculation. Tech. Report UPC-DAC-1996-50, Univ. PolitEcnica de Catalunya, Spain. 1996.
	10	L. Gwennap. Digital 21264 Sets New Standard, Microprocessor Report, 10 (14), Oct. 1996.
	11	G.A.Kemp, M.Franklin, "PEWs: A Decentralized Dynamic Scheduler for ILP Processing, in Proc. of Int. Conf. on Parallel Processing, pp. 239-246, August 1996.
	12	Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	13	Doug Matzke, Will Physical Scalability Sabotage Performance Gains?, Computer, v.30 n.9, p.37-39, September 1997 [doi>10.1109/2.612245]
	14	Mediabench Home Page. URL: http://www.cs.ucla.edu/ ~leec/mediabench/
	15	Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
	16	Subbarao Palacharla , James E. Smith, Complexity-effective superscalar processors, 1998
	17	Eric Rotenberg , Quinn Jacobson , Yiannakis Sazeides , Jim Smith, Trace processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.138-148, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	18	S. Subramanya Sastry , Subbarao Palacharla , James E. Smith, Exploiting idle floating-point resources for integer execution, Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation, p.118-129, June 17-19, 1998, Montreal, Quebec, Canada
	19	Yiannakis Sazeides , Stamatis Vassiliadis , James E. Smith, The performance potential of data dependence speculation & collapsing, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.238-247, December 02-04, 1996, Paris, France
	20	Sriram Vajapeyam , Tulika Mitra, Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences, Proceedings of the 24th annual international symposium on Computer architecture, p.1-12, June 01-04, 1997, Denver, Colorado, United States

CITED BY 7

	Joan-Manuel Parcerisa , Julio Sahuquillo , Antonio Gonzalez , Jose Duato, On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.130-144, February 2005
	Mladen Berekovic , Sören Moch , Peter Pirsch, A scalable, clustered SMT processor for digital signal processing, ACM SIGARCH Computer Architecture News, v.32 n.3, p.62-69, June 2004
	José González , Fernando Latorre , Antonio González, Cache organizations for clustered microarchitectures, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.46-55, June 20-20, 2004, Munich, Germany
	Rajeev Balasubramonian, Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
	Aneesh Aggarwal , Manoj Franklin, Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency, IEEE Transactions on Computers, v.54 n.12, p.1496-1507, December 2005
	Aneesh Aggarwal , Manoj Franklin, Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors, IEEE Transactions on Parallel and Distributed Systems, v.16 n.10, p.944-955, October 2005
	Timothy Mark Pinkston , Jeonghee Shin, Trends toward on-chip networked microsystems, International Journal of High Performance Computing and Networking, v.3 n.1, p.3-18, September 2005