| The store-load address table and speculative register promotion |
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International Symposium on Microarchitecture
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Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
table of contents
Monterey, California, United States
Pages: 235 - 244
Year of Publication: 2000
ISBN:1-58113-196-8
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Authors
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Matthew Postiff
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Advanced Computer Architecture Laboratory, University of Michigan, 1301 Beal Ave., Ann Arbor, MI
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David Greene
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Advanced Computer Architecture Laboratory, University of Michigan, 1301 Beal Ave., Ann Arbor, MI
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Trevor Mudge
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Advanced Computer Architecture Laboratory, University of Michigan, 1301 Beal Ave., Ann Arbor, MI
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| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 24, Citation Count: 7
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Alexander Klaiber. The Technology Behind Crusoe TM Processors. Transmeta Corporation. January 2000.
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Raymond Lo , Fred Chow , Robert Kennedy , Shin-Ming Liu , Peng Tu, Register promotion by sparse partial redundancy elimination of loads and stores, Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation, p.26-37, June 17-19, 1998, Montreal, Quebec, Canada
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Malcom J. Wing and Edmund J. Kelly, Transmeta Corporation. Method and apparatus for aliasing memory data in an advanced microprocessor. United States Patent 5926832. http://www.patents. ibm.com.
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David Bernstein, Martin E. Hopkins, and Michael Rodeh, International Business Machines Corporation. Speculative Load Instruction Rescheduler for a Compiler Which Moves Load Instructions Across Basic Block Boundaries While Avoiding Program Exceptions. United States Patent 5526499. http:// www.patents.ibm.com.
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Tokuzo Kiyohara, Wen-mei W. Hwu; William Chen, Matsushita Electric Industrial Co., Ltd., and The Board of Trustees of the University of Illinois. Memory conflict buffer for achieving memory disambiguation in compile-time code schedule. United States Patent 5694577. http://www.patents.ibm.com.
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Douglas C. Burger and Todd M. Austin. The SimpleScalar Tool Set, Version 2.0. University of Wisconsin, Madison Tech. Report. June, 1997.
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UNIX System Laboratories Inc. System V Application Binary Interface: MIPS Processor Supplement. Unix Press/Prentice Hall, Englewood Cliffs, New Jersey, 1991.
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Matthew Postiff, David Greene, Charles Lefurgy, Dave Helder, Trevor Mudge. The MIRV SimpleScalar/PISA Compiler. University of Michigan CSE Technical Report CSE-TR-421-00. http:// www.eecs.umich.edu/mirv.
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Intel IA-64 Application Developer's Architecture Guide. May 1999. Order Number: 245188-001.
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H. Roland Kenner, Alan Karp, and William Chen, Institute for the Develoment of Emerging Architecture, L.L.C. Method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs. United States Patent 5903749. http://www.patents.ibm.com.
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Robert Yung and Neil C. Wilhelm. Caching Processor General Registers. Sun Microsystems Laboratories Tech. Report. June, 1995.
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Matthew Postiff, David Greene, and Trevor Mudge. Exploiting Large Register Files in General Purpose Code. University of Michigan Technical Report CSE-TR-434-00. http:// www.eecs.umich.edu/mirv.
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CITED BY 7
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Markus Mock , Manuvir Das , Craig Chambers , Susan J. Eggers, Dynamic points-to sets: a comparison with static analyses and potential applications in program understanding and optimization, Proceedings of the 2001 ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering, p.66-72, June 2001, Snowbird, Utah, United States
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