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Register integration: a simple and efficient implementation of squash reuse

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 223 - 234

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Amir Roth	Computer Sciences Department, University of Wisconsin-Madison
Gurindar S. Sohi	Computer Sciences Department, University of Wisconsin-Madison

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 18, Citation Count: 12

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. Burger and T. Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin-Madison, Jun. 1997.
	2	Yuan Chou , Jason Fung , John Paul Shen, Reducing branch misprediction penalties via dynamic control independence detection, Proceedings of the 13th international conference on Supercomputing, p.109-118, June 20-25, 1999, Rhodes, Greece [doi>10.1145/305138.305175]
	3	George Z. Chrysos , Joel S. Emer, Memory dependence prediction using store sets, Proceedings of the 25th annual international symposium on Computer architecture, p.142-153, June 27-July 02, 1998, Barcelona, Spain
	4	José-Lorenzo Cruz , Antonio González , Mateo Valero , Nigel P. Topham, Multiple-banked register file architectures, Proceedings of the 27th annual international symposium on Computer architecture, p.316-325, June 2000, Vancouver, British Columbia, Canada
	5	K. Diefendorf. K7 Challenges Intel. Microprocessor Report, 12(14), Nov. 1998.
	6	K. Diefendorf. Compaq Chooses SMT for Alpha. Microprocessor Report, 13(16), Dec. 1999.
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	8	Manoj Franklin, The multiscalar architecture, University of Wisconsin at Madison, Madison, WI, 1993
	9	P. Glaskowsky. Pentium 4 (Partially) Previewed. Microprocessor Report, 14(8), Aug. 2000.
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	12	Mikko Herman Lipasti, Value locality and speculative execution, Carnegie Mellon University, Pittsburgh, PA, 1998
	13	Srilatha Manne , Artur Klauser , Dirk Grunwald, Pipeline gating: speculation control for energy reduction, Proceedings of the 25th annual international symposium on Computer architecture, p.132-141, June 27-July 02, 1998, Barcelona, Spain
	14	A. Moshovos and G. Sohi. Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. In Proc. 6th Annual International Symposium on High-Performance Computer Architecture, pages 301-312, Feb. 2000.
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	16	Eric Rotenberg , Jim Smith, Control independence in trace processors, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.4-15, November 16-18, 1999, Haifa, Israel
	17	Amir Roth , Gurindar S. Sohi, Speculative Data-Driven Multithreading, Proceedings of the 7th International Symposium on High-Performance Computer Architecture, p.37, January 20-24, 2001
	18	Avinash Sodani , Gurindar S. Sohi, Dynamic instruction reuse, Proceedings of the 24th annual international symposium on Computer architecture, p.194-205, June 01-04, 1997, Denver, Colorado, United States
	19	P. Song. IBM's Power3 to Replace P2SC. Microprocessor Report, 11(15), Nov. 1997.
	20	Dean M. Tullsen , Susan J. Eggers , Henry M. Levy, Simultaneous multithreading: maximizing on-chip parallelism, Proceedings of the 22nd annual international symposium on Computer architecture, p.392-403, June 22-24, 1995, S. Margherita Ligure, Italy
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CITED BY 12

	Peng Zhou , Soner Õnder, Improving single-thread performance with fine-grain state maintenance, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy
	Robert S. Chappell , Francis Tseng , Adi Yoaz , Yale N. Patt, Difficult-path branch prediction using subordinate microthreads, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Haitham Akkary , Srikanth T. Srinivasan , Konrad Lai, Recycling waste: exploiting wrong-path execution to improve branch prediction, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA
	Craig Zilles , Gurindar Sohi, Execution-based prediction using speculative slices, ACM SIGARCH Computer Architecture News, v.29 n.2, p.2-13, May 2001
	Vlad Petric , Anne Bracy , Amir Roth, Three extensions to register integration, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Jamison D. Collins , Dean M. Tullsen , Hong Wang, Control Flow Optimization Via Dynamic Reconvergence Prediction, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.129-140, December 04-08, 2004, Portland, Oregon
	Deniz Balkan , Joseph Sharkey , Dmitry Ponomarev , Kanad Ghose, SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
	Amir Roth, Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization, ACM SIGARCH Computer Architecture News, v.33 n.2, p.458-468, May 2005
	Vlad Petric , Tingting Sha , Amir Roth, RENO: A Rename-Based Instruction Optimizer, ACM SIGARCH Computer Architecture News, v.33 n.2, p.98-109, May 2005
	G. Surendra , Subhasis Banerjee , S. K. Nandy, Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations, Journal of Embedded Computing, v.2 n.1, p.15-34, January 2006
	Mayank Agarwal , Nitin Navale , Kshitiz Malik , Matthew I. Frank, Fetch-Criticality Reduction through Control Independence, ACM SIGARCH Computer Architecture News, v.36 n.3, p.13-24, June 2008
	Deniz Balkan , Joseph Sharkey , Dmitry V. Ponomarev , Kanad Ghose, Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption, IEEE Transactions on Computers, v.57 n.1, p.82-95, January 2008