Dynamic zero compression for cache energy reduction

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Dynamic zero compression for cache energy reduction

Full text

Publisher Site , Pdf

Pdf (91 KB),

Ps (520 KB)

Source

International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 214 - 220

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Luis Villa	MIT Laboratory for Computer science, Cambridge, MA
Michael Zhang	MIT Laboratory for Computer science, Cambridge, MA
Krste Asanović	MIT Laboratory for Computer science, Cambridge, MA

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 37, Citation Count: 33

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/360128.360150 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	B. Amrutur and M. Horowitz. Techniques to reduce power in fast wide memories. In Symposium on Low Power Electronics, volume 1, pages 92-93, October 1994.
	2	C. Benveniste, P. Franaszek, and J. Robinson. Cachememory nterfaces in compressed memory systems. In Solving the Memory Wall Problem Workshop, ISCA-27, Vancouver, Canada, June 2000.
	3	David Brooks , Margaret Martonosi, Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.13, January 09-12, 1999
	4	Standard Performance Evaluation Corporation. Spec95, 1995. http://www.spec.org
	5	S. Santhanam et. al. A low-cost, 300-MHz, RISC CPU with attached media processor. IEEE Journal of Solid-State Circuits, 33(11):1829-1838, November 1998.
	6	Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313860]
	7	R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid State Circuits, 31(9):1277-1284, September 1996.
	8	Chunho Lee , Miodrag Potkonjak , William H. Mangione-Smith, MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.330-335, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	9	M. Panich. Reducing instruction cache energy using gated wordlines. Master's thesis, Massachusetts Institute of Technology, August 1999.
	10	J. H. Tseng , K. Asanovic, Energy-Efficient Register Access, Proceedings of the 13th symposium on Integrated circuits and systems design, p.377, September 18-24, 2000
	11	N. Vijaykrishnan , M. Kandemir , M. J. Irwin , H. S. Kim , W. Ye, Energy-driven integrated hardware-software optimizations using SimplePower, Proceedings of the 27th annual international symposium on Computer architecture, p.95-106, June 2000, Vancouver, British Columbia, Canada
	12	You-Sung Chang , Bong-Il Park , Chong-Min Kyung, Conforming inverted data store for low power memory, Proceedings of the 1999 international symposium on Low power electronics and design, p.91-93, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313871]

CITED BY 33

	Seongmoo Heo , Kenneth Barr , Mark Hampton , Krste Asanović, Dynamic fine-grain leakage reduction using leakage-biased bitlines, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Jun Yang , Rajiv Gupta, Energy efficient frequent value data cache design, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Jun Yang , Rajiv Gupta, Frequent value locality and its applications, ACM Transactions on Embedded Computing Systems (TECS), v.1 n.1, p.79-105, November 2002
	Vasily G. Moshnyaga , Koji Inoue , Mizuka Fukagawa, Reducing energy consumption of video memory by bit-width compression, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Takanori Okuma , Yun Cao , Masanori Muroyama , Hiroto Yasuura, Reducing access energy of on-chip data memory considering active data bitwidth, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Gurhan Kucuk , Kanad Ghose , Dimitry V. Ponomarev , Peter M. Kogge, Energy: efficient instruction dispatch buffer design for superscalar processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.237-242, August 2001, Huntington Beach, California, United States
	Vasily Moshnyaga, Energy reduction in queues and stacks by adaptive bitwidth compression, Proceedings of the 2001 international symposium on Low power electronics and design, p.22-27, August 2001, Huntington Beach, California, United States
	Gabriel H. Loh, Exploiting data-width locality to increase superscalar execution bandwidth, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Carlos Molina , Carles Aliagas , Montse García , Antonio Gonzàlez , Jordi Tubella, Non redundant data cache, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Dmitry V. Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose , Peter M. Kogge, Energy-efficient issue queue design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.789-800, October 2003
	Yen-Jen Chang , Chia-Lin Yang , Feipei Lai, A power-aware SWDR cell for reducing cache write power, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Raksit Ashok , Saurabh Chheda , Csaba Andras Moritz, Coupling compiler-enabled and conventional memory accessing for energy efficiency, ACM Transactions on Computer Systems (TOCS), v.22 n.2, p.180-213, May 2004
	Yen-Jen Chang , Feipei Lai , Chia-Lin Yang, Zero-aware asymmetric SRAM cell for reducing cache power in writing zero, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.8, p.827-836, August 2004
	Michael Zhang , Krste Asanović, Fine-grain CAM-tag cache resizing using miss tags, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Erik G. Hallnor , Steven K. Reinhardt, A compressed memory hierarchy using an indirect index cache, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.9-15, June 20-20, 2004, Munich, Germany
	Yen-Jen Chang , Feipei Lai, Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories, IEEE Micro, v.25 n.4, p.20-32, July 2005
	Nihar R. Mahapatra , Jiangjiang Liu , Krishnan Sundaresan, The performance advantage of applying compression to the memory system, ACM SIGPLAN Notices, v.38 n.2 supplement, p.86-96, February 2003
	Kimish Patel , Enrico Macii , Massimo Poncino, Zero clustering: an approach to extend zero compression to instruction caches, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	R. González , A. Cristal , M. Pericas , M. Valero , A. Veidenbaum, An asymmetric clustered processor based on value content, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts
	Andreas Moshovos , Babak Falsafi , Farid N. Najm , Navid Azizi, A case for asymmetric-cell cache memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.877-881, July 2005
	Ramon Canal , Antonio González , James E. Smith, Software-Controlled Operand-Gating, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, p.125, March 20-24, 2004, Palo Alto, California
	Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon
	Kaveh Jokar Deris , Amirali Baniasadi, Investigating cache energy and latency break-even points in high performance processors, Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, p.13-20, September 16-20, 2006, Seattle, Washington
	Prateek Pujara , Aneesh Aggarwal, Increasing cache capacity through word filtering, Proceedings of the 21st annual international conference on Supercomputing, June 17-21, 2007, Seattle, Washington
	Gonzalez Gonzalez , Adrian Cristal , Daniel Ortega , Alexander Veidenbaum , Mateo Valero, A Content Aware Integer Register File Organization, ACM SIGARCH Computer Architecture News, v.32 n.2, p.314, March 2004
	Mirko Loghi , Paolo Azzoni , Massimo Poncino, Tag Overflow Buffering: An Energy-Efficient Cache Architecture, Proceedings of the conference on Design, Automation and Test in Europe, p.520-525, March 07-11, 2005
	Yen-Jen Chang , Chia-Lin Yang , Feipei Lai, Value-Conscious Cache: Simple Technique for Reducing Cache Access Power, Proceedings of the conference on Design, automation and test in Europe, p.10016, February 16-20, 2004
	Marco A. Ramirez , Adrian Cristal , Mateo Valero , Alexander V. Veidenbaum , Luis Villa, A partitioned instruction queue to reduce instruction wakeup energy, International Journal of High Performance Computing and Networking, v.1 n.4, p.153-161, December 2004
	Kaveh Jokar Deris , Amirali Baniasadi, Investigating cache energy and latency break-even points in high performance processors, ACM SIGARCH Computer Architecture News, v.35 n.4, September 2007
	Wangyuan Zhang , Tao Li, Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.435-446, November 08-12, 2008
	Mafijul Md. Islam , Per Stenstrom, Zero loads: canceling load requests by tracking zero values, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.16-23, October 26-26, 2008, Toronto, Canada
	Julien Dusser , Thomas Piquet , André Seznec, Zero-content augmented caches, Proceedings of the 23rd international conference on Supercomputing, June 08-12, 2009, Yorktown Heights, NY, USA
	Rachita Kothiyal , Vasily Tarasov , Priya Sehgal , Erez Zadok, Energy and performance evaluation of lossless file data compression on server systems, Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference, May 04-April 06, 2009, Haifa, Israel