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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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2
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S. Altschul, W. Gish, W. Miller, E. Myers, and D. Lipman. Basic Local Alignment Search Tool. Journal of Molecular Biology, 215(3):403- 410, October 1990.
|
| |
3
|
J. Alvarez et al. A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors. IEEE Journal on Solid-State Circuits, 30(4):383- 391, April 1995.
|
| |
4
|
Luca Benini , Alessandro Bogliolo , Stefano Cavallucci , Bruno Riccó, Monitoring system activity for OS-directed dynamic power management, Proceedings of the 1998 international symposium on Low power electronics and design, p.185-190, August 10-12, 1998, Monterey, California, United States
[doi> 10.1145/280756.280887]
|
| |
5
|
D. Brooks and M. Martonosi. Adaptive Thermal Management for High-Performance Microprocessors. In Workshop on Complexity Effective Design, June 2000.
|
| |
6
|
|
| |
7
|
|
| |
8
|
S. Ghiasi, J. Casmira, and D. Grunwald. Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption. In Workshop on Complexity-Effective Design, June 2000.
|
| |
9
|
Kanad Ghose , Milind B. Kamble, Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation, Proceedings of the 1999 international symposium on Low power electronics and design, p.70-75, August 16-17, 1999, San Diego, California, United States
[doi> 10.1145/313817.313860]
|
| |
10
|
R. Gonzalez and M. Horowitz. Energy Dissipation In General Purpose Microprocessors. IEEE Journal on Solid-State Circuits, 31(4):1277- 1284, September 1996.
|
| |
11
|
T. Halfhill. Transmeta Breaks x86 Low-Power Barrier. Microprocessor Report, 14(2):1,9-18, February 2000.
|
| |
12
|
IBM Microelectronics. Blue Logic SA-27E ASIC. http://www.chips.ibm. com/news/1999/sa27e/sa27e.pdf, February 1999.
|
| |
13
|
Intel. Pentium III Processor Mobile Module: Mobile Module Connector 2 (MMC-2) Featuring Intel SpeedStep Technology, 2000.
|
| |
14
|
Intel, Microsoft and Toshiba. Advanced Configuration and Power Interface Specification, 1999.
|
| |
15
|
K. Itoh. Low Power Memory Design. In Low Power Design Methodologies, pages 201-251. Kluwer Academic Publisher, 1996.
|
| |
16
|
K. Itoh et al. An Experimental 1Mb DRAM with On-Chip Voltage Limiter. In ISSCC Digest of Technical Papers, pages 84-85, February 1981.
|
| |
17
|
Toni Juan , Tomas Lang , Juan J. Navarro, Reducing TLB power requirements, Proceedings of the 1997 international symposium on Low power electronics and design, p.196-201, August 18-20, 1997, Monterey, California, United States
[doi> 10.1145/263272.263332]
|
| |
18
|
|
| |
19
|
|
| |
20
|
Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
| |
21
|
|
| |
22
|
R. Lawrence, G. Almasi, and H. Rushmeier. A Scalable Parallel Algorithm for Self-Organizing Maps with Applications to Sparse Data Mining Problems. Technical report, IBM, January 1998.
|
| |
23
|
|
| |
24
|
J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. IEEE Journal Solid State Circuits, 31(11):1703-1714, November 1996.
|
| |
25
|
Trevor Pering , Tom Burd , Robert Brodersen, The simulation and evaluation of dynamic voltage scaling algorithms, Proceedings of the 1998 international symposium on Low power electronics and design, p.76-81, August 10-12, 1998, Monterey, California, United States
[doi> 10.1145/280756.280790]
|
| |
26
|
|
| |
27
|
E. Rohou and M. Smith. Dynamically Managing Processor Temperatureand Power. In 2nd Workshop on Feedback-Directed Optimization, November 1999.
|
| |
28
|
Hector Sanchez , Belli Kuttanna , Tim Olson , Mike Alexander , Gian Gerosa , Ross Philip , Jose Alvarez, Thermal Management System for High Performance PowerPCTM Microprocessors, Proceedings of the 42nd IEEE International Computer Conference, p.325, February 23-26, 1997
|
| |
29
|
S. Sidiropoulos and M. Horowitz. A Semidigital Dual Delay-Locked Loop. IEEE Journal on Solid-state Circuits, 32(11):1683-1692, November 1997.
|
| |
30
|
|
| |
31
|
C-H. Tsai. Temperature-Aware VLSI Design and Analysis. PhD thesis, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, May 2000.
|
| |
32
|
|
| |
33
|
N. Vijaykrishnan , M. Kandemir , M. J. Irwin , H. S. Kim , W. Ye, Energy-driven integrated hardware-software optimizations using SimplePower, Proceedings of the 27th annual international symposium on Computer architecture, p.95-106, June 2000, Vancouver, British Columbia, Canada
|
| |
34
|
S. Wilton and N. Jouppi. CACTI: An Enhanced Cache Access and Cycle Time Model. IEEE Journal on Solid-State Circuits, 31(5):677- 688, May 1996.
|
| |
35
|
N. Yeung. et al. The Design of a 55SPECint92 RISC Processor under 2W. ISSCC Digest of Technical Papers, pages 206-207, February 1994.
|
| |
36
|
S-M. Yoo, J. Renau, M. Huang, and J. Torrellas. FlexRAM Architecture Design Parameters. Technical Report CSRD-1584, Department of Computer Science, University of Illinois at Urbana-Champaign, October 2000. http://iacoma.cs.uiuc.edu/flexram/publications.html.
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CITED BY 43
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Christopher J. Hughes , Praful Kaul , Sarita V. Adve , Rohit Jain , Chanik Park , Jayanth Srinivasan, Variability in the execution of multimedia applications and implications for architecture, ACM SIGARCH Computer Architecture News, v.29 n.2, p.254-265, May 2001
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Kevin Skadron , Mircea R. Stan , Karthik Sankaranarayanan , Wei Huang , Sivakumar Velusamy , David Tarjan, Temperature-aware microarchitecture: Modeling and implementation, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.1, p.94-125, March 2004
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G. Paci , P. Marchal , F. Poletti , L. Benini, Exploring "temperature-aware" design in low-power MPSoCs, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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David Atienza , Pablo G. Del Valle , Giacomo Paci , Francesco Poletti , Luca Benini , Giovanni De Micheli , Jose M. Mendias, A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Michael Healy , Mario Vittes , Mongkol Ekpanyapong , Chinnakrishnan Ballapuram , Sung Kyu Lim , Hsien-Hsin S. Lee , Gabriel H. Loh, Microarchitectural floorplanning under performance and thermal tradeoff, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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Amit Kumar , Li Shang , Li-Shiuan Peh , Niraj K. Jha, HybDTM: a coordinated hardware-software approach for dynamic thermal management, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
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Srinivasan Murali , Almir Mutapcic , David Atienza , Rajesh Gupta , Stephen Boyd , Giovanni De Micheli, Temperature-aware processor frequency assignment for MPSoCs using convex optimization, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis, September 30-October 03, 2007, Salzburg, Austria
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Ke Meng , Russ Joseph , Robert P. Dick , Li Shang, Multi-optimization power management for chip multiprocessors, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, October 25-29, 2008, Toronto, Ontario, Canada
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