A static power model for architects

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	David H. Albonesi, Selective cache ways: on-demand cache resource allocation, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.248-259, November 16-18, 1999, Haifa, Israel
	2	Todd M. Austin, DIVA: a reliable substrate for deep submicron microarchitecture design, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.196-207, November 16-18, 1999, Haifa, Israel
	3	R. Iris Bahar , Gianluca Albera , Srilatha Manne, Power and performance tradeoffs using various caching strategies, Proceedings of the 1998 international symposium on Low power electronics and design, p.64-69, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.295115]
	4	D. T. Blaauw , A. Dharchoudhury , R. Panda , S. Sirichotiyakul , C. Oh , T. Edwards, Emerging power management tools for processor design, Proceedings of the 1998 international symposium on Low power electronics and design, p.143-148, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280866]
	5	David Brooks , Margaret Martonosi, Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.13, January 09-12, 1999
	6	David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
	7	B. Davari. CMOS Technology Scaling, 0.1 mm and Beyond. In Proceedings of the International Electron Devices Meeting, 1996. pp. 555-558.
	8	Vivek De , Shekhar Borkar, Technology and design challenges for low power and high performance, Proceedings of the 1999 international symposium on Low power electronics and design, p.163-168, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313908]
	9	R. Dennard, F. Gaensslen, H. Yu, V. Rideout, E. Bassous, and A. LeBlanc. Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions. IEEE Journal of Solid-State Circuits, 9(5), October 1974. pp. 256-268.
	10	P. Glaskowsky. Pentium 4 (Partially) Previewed. Microprocessor Report, August 28, 2000.
	11	R. Gonzalez and M. Horowitz. Energy Dissipation in General Purpose Microprocessors. IEEE Journal of Solid- State ircuits, 31(9), September 1996. pp. 1277-1284.
	12	M. Horowitz, T. Indermaur, and R. Gonzalez. Low-Power Digital Design. In Proceedings of the 1994 IEEE Symposium on Low Power Electronics. pp. 8-11.
	13	Intel Corporation. Pentium III Processor for the SC242 at 450 MHz to 1.13 GHz Datasheet. pp. 26-30.
	14	M. Johnson, D. Somasekhar, and K. Roy. Models and Algorithms for Bounds on Leakage in CMOS Circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 18(6), June 1999. pp. 714-725.
	15	Ali Keshavarzi , Kaushik Roy , Charles F. Hawkins, Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs, Proceedings of the IEEE International Test Conference, p.146-155, November 03-05, 1997
	16	Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	17	P. Ko, J. Huang, Z. Liu, and C. Hu. BSIM3 for Analog and Digital Circuit Simulation. In Proceedings of the IEEE Symposium on VLSI Technology CAD, January 1993. pp. 400-429.
	18	K. Krewell. Quicktake: Willamette Revealed. Microprocessor Report, February 2000. p. 19.
	19	Srilatha Manne , Artur Klauser , Dirk Grunwald, Pipeline gating: speculation control for energy reduction, Proceedings of the 25th annual international symposium on Computer architecture, p.132-141, June 27-July 02, 1998, Barcelona, Spain
	20	H. Massalin , C. Pu, Threads and input/output in the synthesis kernal, Proceedings of the twelfth ACM symposium on Operating systems principles, p.191-201, November 1989
	21	E. Nowak. Ultimate CMOS ULSI Performance. In Proceedings of the International Electron Devices Meeting, 1993. pp. 115-118.
	22	Michael Powell , Se-Hyun Yang , Babak Falsafi , Kaushik Roy , T. N. Vijaykumar, Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories, Proceedings of the 2000 international symposium on Low power electronics and design, p.90-95, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344526]
	23	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	24	K. Roy. Leakage Power Reduction in Low-Voltage CMOS Design. In Proceedings of the IEEE International Conference on Circuits and Systems, 1998. pp. 167-173.
	25	Takayasu Sakurai , Hiroshi Kawaguchi , Tadahiro Kuroda, Low-power CMOS design through VTH control and low-swing circuits, Proceedings of the 1997 international symposium on Low power electronics and design, p.1-6, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263273]
	26	T. Sakurai and A. Newton. Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas. IEEE Journal of Solid-State Circuits, 25(4), April 1990. pp. 584-594.
	27	Semiconductor Industry Association. International Technology Roadmap for Semiconductors, 1999 edition. Austin, TX: SEMATECH, 1999.
	28	Ching-Long Su , A. M. Despain, Cache designs for energy efficiency, Proceedings of the 28th Hawaii International Conference on System Sciences (HICSS'95), p.306, January 04-07, 1995
	29	Vijay Sundararajan , Keshab K. Parhi, Low power synthesis of dual threshold voltage CMOS VLSI circuits, Proceedings of the 1999 international symposium on Low power electronics and design, p.139-144, August 16-17, 1999, San Diego, California, United States [doi>10.1145/313817.313900]
	30	S. Sze. Physics of Semiconductor Devices, 2nd. Ed. John Wiley and Sons, 1981.
	31	Vivek Tiwari , Ryan Donnelly , Sharad Malik , Ricardo Gonzalez, Dynamic Power Management for Microprocessors: A Case Study, Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications, p.185, January 04-07, 1997
	32	Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277227]
	33	Y. Taur and E. Nowak. CMOS Devices Below 0.1 mm: How High Will Performance Go? In Proceedings of the International Electron Devices Meeting, 1997. pp. 215- 218.
	34	S. Thompson, P. Packan, and M. Bohr. MOS Scaling: Transistor Challenges for the 21st Century. Intel Technology Journal, Q3 1998.
	35	N. Vijaykrishnan , M. Kandemir , M. J. Irwin , H. S. Kim , W. Ye, Energy-driven integrated hardware-software optimizations using SimplePower, Proceedings of the 27th annual international symposium on Computer architecture, p.95-106, June 2000, Vancouver, British Columbia, Canada
	36	Qi Wang , Sarma B. K. Vrudhula, Static power optimization of deep submicron CMOS circuits for dual VT technology, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.490-496, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.289076]
	37	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	38	D. Wouters, J. Colinge, H. Maes. Subthreshold Slope in Thin-Film SOI MOSFET's. IEEE Transactions on Electron Devices, 37(9), September 1990. pp. 2022-2033.