Very low power pipelines using significance compression

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Very low power pipelines using significance compression

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 181 - 190

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Ramon Canal	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona
Antonio González	Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, Barcelona
James E. Smith	Department of Electrical and Computing Eng., University of Wisconsin-Madison

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 56, Citation Count: 21

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 21

	Gurhan Kucuk , Kanad Ghose , Dimitry V. Ponomarev , Peter M. Kogge, Energy: efficient instruction dispatch buffer design for superscalar processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.237-242, August 2001, Huntington Beach, California, United States
	Vasily Moshnyaga, Energy reduction in queues and stacks by adaptive bitwidth compression, Proceedings of the 2001 international symposium on Low power electronics and design, p.22-27, August 2001, Huntington Beach, California, United States
	Daniele Folegnani , Antonio González, Energy-effective issue logic, ACM SIGARCH Computer Architecture News, v.29 n.2, p.230-239, May 2001
	Jun Yang , Rajiv Gupta, Energy efficient frequent value data cache design, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Dmitry V. Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose , Peter M. Kogge, Energy-efficient issue queue design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.789-800, October 2003
	Carlos Molina , Carles Aliagas , Montse García , Antonio Gonzàlez , Jordi Tubella, Non redundant data cache, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Gilles Pokam , Olivier Rochecouste , André Seznec , François Bodin, Speculative software management of datapath-width for energy optimization, ACM SIGPLAN Notices, v.39 n.7, July 2004
	Sunan Tugsinavisut , Youpyo Hong , Daewook Kim , Kyeounsoo Kim , Peter A. Beerel, Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.4, p.448-461, April 2005
	R. González , A. Cristal , M. Pericas , M. Valero , A. Veidenbaum, An asymmetric clustered processor based on value content, Proceedings of the 19th annual international conference on Supercomputing, June 20-22, 2005, Cambridge, Massachusetts
	DongRui Fan , HongBo Yang , GuangRong Gao , RongCai Zhao, Evaluation and choice of various branch predictors for low-power embedded processor, Journal of Computer Science and Technology, v.18 n.6, p.833-838, November 2003
	Jun Yang , Jia Yu , Youtao Zhang, A low energy cache design for multimedia applications exploiting set access locality, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.10-11, p.653-664, October/November 2005
	Andreas Moshovos , Babak Falsafi , Farid N. Najm , Navid Azizi, A case for asymmetric-cell cache memories, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.877-881, July 2005
	Ramon Canal , Antonio González , James E. Smith, Software-Controlled Operand-Gating, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, p.125, March 20-24, 2004, Palo Alto, California
	Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon
	Kaushal R. Gandhi , Nihar R. Mahapatra, Exploiting data-dependent slack using dynamic multi-VDD to minimize energy consumption in datapath circuits, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Olivier Rochecouste , Gilles Pokam , André Seznec, A case for a complexity-effective, width-partitioned microarchitecture, ACM Transactions on Architecture and Code Optimization (TACO), v.3 n.3, p.295-326, September 2006
	Mikko H. Lipasti , Brian R. Mestan , Erika Gunadi, Physical Register Inlining, ACM SIGARCH Computer Architecture News, v.32 n.2, p.325, March 2004
	Gonzalez Gonzalez , Adrian Cristal , Daniel Ortega , Alexander Veidenbaum , Mateo Valero, A Content Aware Integer Register File Organization, ACM SIGARCH Computer Architecture News, v.32 n.2, p.314, March 2004
	Amir Hormati , Nathan Clark , Scott Mahlke, Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping, Proceedings of the International Symposium on Code Generation and Optimization, p.341-353, March 11-14, 2007
	Mafijul Md. Islam , Magnus Själander , Per Stenström, Early detection and bypassing of trivial operations to improve energy efficiency of processors, Microprocessors & Microsystems, v.32 n.4, p.183-196, June, 2008
	Wangyuan Zhang , Tao Li, Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.435-446, November 08-12, 2008