PipeRench implementation of the instruction path coprocessor

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PipeRench implementation of the instruction path coprocessor

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 147 - 158

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Yuan Chou	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Pazhani Pillai	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
Herman Schmit	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA
John Paul Shen	Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 39, Citation Count: 6

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	4	Seth Copen Goldstein , Herman Schmit , Matthew Moe , Mihai Budiu , Srihari Cadambi , R. Reed Taylor , Ronald Laufer, PipeRench: a co/processor for streaming multimedia acceleration, Proceedings of the 26th annual international symposium on Computer architecture, p.28-39, May 01-04, 1999, Atlanta, Georgia, United States
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CITED BY 6

	Domingo Benitez, Performance of reconfigurable architectures for image-processing applications, Journal of Systems Architecture: the EUROMICRO Journal, v.49 n.4-6, p.193-210, September 2003
	Nathan Clark , Manjunath Kudlur , Hyunchul Park , Scott Mahlke , Krisztian Flautner, Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.30-40, December 04-08, 2004, Portland, Oregon
	Stephan Gatzka , Christian Hochberger, The AMIDAR Class of Reconfigurable Processors, The Journal of Supercomputing, v.32 n.2, p.163-181, May 2005
	Sami Yehia , Olivier Temam, From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation, ACM SIGARCH Computer Architecture News, v.32 n.2, p.238, March 2004
	Sebastian Lange , Udo Kebschull, Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems, Proceedings of the conference on Design, Automation and Test in Europe, p.10302, March 03-07, 2003
	Tameesh Suri , Aneesh Aggarwal, Improving performance of simple cores by exploiting loop-level parallelism through value prediction and reconfiguration, Proceedings of the 6th ACM conference on Computing frontiers, May 18-20, 2009, Ischia, Italy