Two-level hierarchical register file organization for VLIW processors

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Two-level hierarchical register file organization for VLIW processors

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 137 - 146

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Javier Zalamea	Departament d'Arquitectura de Computadors (UPC), Universitat Politécnica de Catalunya
Josep Llosa	Departament d'Arquitectura de Computadors (UPC), Universitat Politécnica de Catalunya
Eduard Ayguadé	Departament d'Arquitectura de Computadors (UPC), Universitat Politécnica de Catalunya
Mateo Valero	Departament d'Arquitectura de Computadors (UPC), Universitat Politécnica de Catalunya

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 7, Downloads (12 Months): 54, Citation Count: 22

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REFERENCES

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	Nam Sung Kim , Trevor Mudge, The microarchitecture of a low power register file, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Alvin R. Lebeck , Jinson Koppanalil , Tong Li , Jaidev Patwardhan , Eric Rotenberg, A large, fast instruction window for tolerating cache misses, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Xiaotong Zhuang , Tao Zhang , Santosh Pande, Hardware-managed register allocation for embedded processors, ACM SIGPLAN Notices, v.39 n.7, July 2004
	Teresa Monreal , Victor Vinals , Jose Gonzalez , Antonio Gonzalez , Mateo Valero, Late Allocation and Early Release of Physical Registers, IEEE Transactions on Computers, v.53 n.10, p.1244-1259, October 2004
	Xiaotong Zhuang , Santosh Pande, Differential register allocation, ACM SIGPLAN Notices, v.40 n.6, June 2005
	Il Park , Michael D. Powell , T. N. Vijaykumar, Reducing register ports for higher speed and lower energy, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Javier Zalamea , Josep Llosa , Eduard Ayguadé , Mateo Valero, Software and hardware techniques to optimize register file utilization in VLIW architectures, International Journal of Parallel Programming, v.32 n.6, p.447-474, December 2004
	Rajeev Balasubramonian , Sandhya Dwarkadas , David H. Albonesi, Reducing the complexity of the register file in dynamic superscalar processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	José F. Martínez , Jose Renau , Michael C. Huang , Milos Prvulovic , Josep Torrellas, Cherry: checkpointed early resource recycling in out-of-order microprocessors, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Nam Sung Kim , Trevor Mudge, Reducing register ports using delayed write-back queues and operand pre-fetch, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA
	Gao Song, Reducing register pressure through LAER algorithm, Proceedings of the 27th Australasian conference on Computer science, p.55-64, January 01, 2004, Dunedin, New Zealand
	Albert Meixner , Daniel J. Sorin, Unified microprocessor core storage, Proceedings of the 4th international conference on Computing frontiers, May 07-09, 2007, Ischia, Italy
	Hua Yang , Gang Cui , Hong-Wei Liu , Xiao-Zong Yang, Compacting register file via 2-level renaming and bit-partitioning, Microprocessors & Microsystems, v.31 n.3, p.178-187, May, 2007
	Xiaotong Zhuang , Santosh Pande, Allocating architected registers through differential encoding, ACM Transactions on Programming Languages and Systems (TOPLAS), v.29 n.2, p.9-es, April 2007
	J. Adam Butts , Gurindar S. Sohi, Use-Based Register Caching with Decoupled Indexing, ACM SIGARCH Computer Architecture News, v.32 n.2, p.302, March 2004
	Mikko H. Lipasti , Brian R. Mestan , Erika Gunadi, Physical Register Inlining, ACM SIGARCH Computer Architecture News, v.32 n.2, p.325, March 2004
	Arvind Krishnaswamy , Rajiv Gupta, Efficient Use of Invisible Registers in Thumb Code, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, p.30-42, November 12-16, 2005, Barcelona, Spain
	Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan, Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.423, December 03-05, 2003
	Shuai Wang , Hongyan Yang , Jie Hu , Sotirios G. Ziavras, Asymmetrically banked value-aware register files for low-energy and high-performance, Microprocessors & Microsystems, v.32 n.3, p.171-182, May, 2008
	Eric P. Villasenor , DaeHo Seo , Mithuna S. Thottethodi, Power-efficient clustering via incomplete bypassing, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Francis Tseng , Yale N. Patt, Achieving Out-of-Order Performance with Almost In-Order Complexity, ACM SIGARCH Computer Architecture News, v.36 n.3, p.3-12, June 2008