Modulo scheduling for a fully-distributed clustered VLIW architecture

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Modulo scheduling for a fully-distributed clustered VLIW architecture

Full text

Publisher Site , Pdf

Pdf (184 KB),

Ps (1.05 MB)

Source

International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 124 - 133

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Jesús Sánchez	Dept. of Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain
Antonio González	Dept. of Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 27, Citation Count: 22

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/360128.360142 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Vikas Agarwal , M. S. Hrishikesh , Stephen W. Keckler , Doug Burger, Clock rate versus IPC: the end of the road for conventional microarchitectures, Proceedings of the 27th annual international symposium on Computer architecture, p.248-259, June 2000, Vancouver, British Columbia, Canada
	2	E. Ayguade, C. Barrado, A. Gonzalez, J. Labarta, D. Lopez, S. Moreno, D. Padua, F. Reig, Q. Riera and M. Valero, Ictineo: a Tool for Research on ILP", in Supercomputing'96 (SC'96), Research Exhibit Polaris at Work, 1996
	3	N. Bermudo, X. Vera, A. Gonzalez and J. Llosa, An Efficient Solver for Cache Miss Equations, in Procs. of Int. Symp. on Performance Analysis and System Software, April 2000
	4	Andrea Capitanio , Nikil Dutt , Alexandru Nicolau, Partitioned register files for VLIWs: a preliminary analysis of tradeoffs, Proceedings of the 25th annual international symposium on Microarchitecture, p.292-300, December 01-04, 1992, Portland, Oregon, United States
	5	David E. Culler , Anoop Gupta , Jaswinder Pal Singh, Parallel Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1997
	6	John R. Ellis, Bulldog: a compiler for VLSI architectures, MIT Press, Cambridge, MA, 1986
	7	Marcio Merino Fernandes , Josep Llosa , Nigel Topham, Distributed Modulo Scheduling, Proceedings of the 5th International Symposium on High Performance Computer Architecture, p.130, January 09-12, 1999
	8	Jose Fridman , Zvi Greenfield, The TigerSHARC DSP Architecture, IEEE Micro, v.20 n.1, p.66-76, January 2000 [doi>10.1109/40.820055]
	9	Somnath Ghosh , Margaret Martonosi , Sharad Malik, Cache miss equations: an analytical representation of cache misses, Proceedings of the 11th international conference on Supercomputing, p.317-324, July 07-11, 1997, Vienna, Austria [doi>10.1145/263580.263657]
	10	L. Gwennap, Digital 21264 Sets New Standard, Microprocessor Report, 10(14), Oct. 1996
	11	S. Jang, S. Carr, P. Sweany and D. Kuras, A Code Generation Framework for VLIW Architectures with Partitioned Register Banks, in Procs. of 3rd. Int. Conf. on Massively Parallel Computing Systems, April 1998
	12	David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
	13	M. Lam, Software pipelining: an effective scheduling technique for VLIW machines, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.318-328, June 20-24, 1988, Atlanta, Georgia, United States
	14	Doug Matzke, Will Physical Scalability Sabotage Performance Gains?, Computer, v.30 n.9, p.37-39, September 1997 [doi>10.1109/2.612245]
	15	MAP1000 unfolds at Equator, Microprocessor Report, 12(16), Dec. 1998
	16	Todd C. Mowry , Monica S. Lam , Anoop Gupta, Design and evaluation of a compiler algorithm for prefetching, Proceedings of the fifth international conference on Architectural support for programming languages and operating systems, p.62-73, October 12-15, 1992, Boston, Massachusetts, United States
	17	Erik Nystrom , Alexandre E. Eichenberger, Effective cluster assignment for modulo scheduling, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.103-114, November 1998, Dallas, Texas, United States
	18	Emre Özer , Sanjeev Banerjia , Thomas M. Conte, Unified assign and schedule: a new approach to scheduling for clustered register file microarchitectures, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.308-315, November 1998, Dallas, Texas, United States
	19	Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
	20	B. R. Rau , C. D. Glaeser, Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing, Proceedings of the 14th annual workshop on Microprogramming, p.183-198, December 01-01, 1981, Chatham, Massachusetts, United States
	21	F. Jesús Sánchez , Antonio González, Cache sensitive modulo scheduling, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.338-348, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	22	Jesús Sánchez , Antonio González, The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures, Proceedings of the Proceedings of the 2000 International Conference on Parallel Processing, p.555, August 21-24, 2000
	23	Semiconductor Industry Association, The National Technology Roadmap for Semiconductors: Technology Needs, 1997
	24	Texas Instruments Inc., TMS320C62x/67x CPU and Instruction Set Reference Guide, 1998
	25	X. Vera, J. Llosa, A. Gonzalez and C. Ciuraneta, A Fast Implementation of Cache Miss Equations, in Procs. of the 8th. Int. Workshop on Compilers for Parallel Computers, pp. 319-326, Jan. 2000
	26	V.V. Zyuban, Low-Power High-Performance Superscalar Architectures, PhD Thesis, Dept. of Computer Science and Engineering, University of Notre Dame, Jan. 2000

CITED BY 22

	Enric Gibert , Jesús Sánchez , Antonio González, An interleaved cache clustered VLIW processor, Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, New York, New York, USA
	Osvaldo Colavin , Davide Rizzo, A scalable wide-issue clustered VLIW with a reconfigurable interconnect, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Enric Gibert , Jesús Sánchez , Antonio González, Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, March 23-26, 2003, San Francisco, California
	Tom Vander Aa , Murali Jayapala , Francisco Barat , Geert Deconinck , Rudy Lauwereins , Francky Catthoor , Henk Corporaal, Instruction buffering exploration for low energy VLIWs with instruction clusters, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.824-829, January 27-30, 2004, Yokohama, Japan
	John W. Sias , Hillery C. Hunter , Wen-mei W. Hwu, Enhancing loop buffering of media and telecommunications applications using low-overhead predication, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Rajeev Balasubramonian, Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
	Xavier Vera , Nerina Bermudo , Josep Llosa , Antonio González, A fast and accurate framework to analyze and optimize cache memory behavior, ACM Transactions on Programming Languages and Systems (TOPLAS), v.26 n.2, p.263-300, March 2004
	Enric Gibert , Jesus Sanchez , Antonio Gonzalez, Distributed Data Cache Designs for Clustered VLIW Processors, IEEE Transactions on Computers, v.54 n.10, p.1227-1241, October 2005
	Enric Gibert , Jesús Sánchez , Antonio González, Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Alex Aletà , Josep M. Codina , Jesús Sánchez , Antonio González, Graph-partitioning based instruction scheduling for clustered processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Zhong Wang , Xiaobo Sharon Hu , Edwin H.-M. Sha, Register aware scheduling for distributed cache clustered architecture, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Manjunath Kudlur , Scott Mahlke, Orchestrating the execution of stream programs on multicore platforms, ACM SIGPLAN Notices, v.43 n.6, June 2008
	Hyunchul Park , Kevin Fan , Manjunath Kudlur , Scott Mahlke, Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
	Praveen Raghavan , Andy Lambrechts , Murali Jayapala , Francky Catthoor , Diederik Verkest , Henk Corporaal, Very wide register: an asymmetric register file organization for low power embedded processors, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Surin Kittitornkun , Yu Hen Hu, Efficient implementation of nested-loop multimedia algorithms, EURASIP Journal on Applied Signal Processing, v.2001 n.1, p.129-146, 1 January 2001
	Michael Bedford Taylor , Walter Lee , Jason Miller , David Wentzlaff , Ian Bratt , Ben Greenwald , Henry Hoffmann , Paul Johnson , Jason Kim , James Psota , Arvind Saraf , Nathan Shnidman , Volker Strumpen , Matt Frank , Saman Amarasinghe , Anant Agarwal, Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams, ACM SIGARCH Computer Architecture News, v.32 n.2, p.2, March 2004
	Michael L. Chu , Scott A. Mahlke, Compiler-directed Data Partitioning for Multicluster Processors, Proceedings of the International Symposium on Code Generation and Optimization, p.208-220, March 26-29, 2006
	Satish Pillai , Margarida F. Jacome, Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling, Proceedings of the conference on Design, Automation and Test in Europe, p.10422, March 03-07, 2003
	Kevin Fan , Hyun hul Park , Manjunath Kudlur , S ott Mahlke, Modulo scheduling for highly customized datapaths to increase hardware reusability, Proceedings of the sixth annual IEEE/ACM international symposium on Code generation and optimization, April 05-09, 2008, Boston, MA, USA
	Enric Gibert , Jesús Sánchez , Antonio González, Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.315, December 03-05, 2003
	Hyunchul Park , Kevin Fan , Scott A. Mahlke , Taewook Oh , Heeseok Kim , Hong-seok Kim, Edge-centric modulo scheduling for coarse-grained reconfigurable architectures, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, October 25-29, 2008, Toronto, Ontario, Canada
	Yingchao Zhao , Chun Jason Xue , Minming Li , Bessie Hu, Energy-aware register file re-partitioning for clustered VLIW architectures, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan