Modulo scheduling for a fully-distributed clustered VLIW architecture

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Modulo scheduling for a fully-distributed clustered VLIW architecture

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 124 - 133

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Jesús Sánchez	Dept. of Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain
Antonio González	Dept. of Computer Architecture, Universitat Politècnica de Catalunya, Barcelona, Spain

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

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ACM New York, NY, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 32, Citation Count: 22

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 22

	Enric Gibert , Jesús Sánchez , Antonio González, An interleaved cache clustered VLIW processor, Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, New York, New York, USA
	Osvaldo Colavin , Davide Rizzo, A scalable wide-issue clustered VLIW with a reconfigurable interconnect, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Enric Gibert , Jesús Sánchez , Antonio González, Local scheduling techniques for memory coherence in a clustered VLIW processor with a distributed data cache, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, March 23-26, 2003, San Francisco, California
	Tom Vander Aa , Murali Jayapala , Francisco Barat , Geert Deconinck , Rudy Lauwereins , Francky Catthoor , Henk Corporaal, Instruction buffering exploration for low energy VLIWs with instruction clusters, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.824-829, January 27-30, 2004, Yokohama, Japan
	John W. Sias , Hillery C. Hunter , Wen-mei W. Hwu, Enhancing loop buffering of media and telecommunications applications using low-overhead predication, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Rajeev Balasubramonian, Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
	Xavier Vera , Nerina Bermudo , Josep Llosa , Antonio González, A fast and accurate framework to analyze and optimize cache memory behavior, ACM Transactions on Programming Languages and Systems (TOPLAS), v.26 n.2, p.263-300, March 2004
	Enric Gibert , Jesus Sanchez , Antonio Gonzalez, Distributed Data Cache Designs for Clustered VLIW Processors, IEEE Transactions on Computers, v.54 n.10, p.1227-1241, October 2005
	Enric Gibert , Jesús Sánchez , Antonio González, Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Alex Aletà , Josep M. Codina , Jesús Sánchez , Antonio González, Graph-partitioning based instruction scheduling for clustered processors, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Zhong Wang , Xiaobo Sharon Hu , Edwin H.-M. Sha, Register aware scheduling for distributed cache clustered architecture, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Manjunath Kudlur , Scott Mahlke, Orchestrating the execution of stream programs on multicore platforms, ACM SIGPLAN Notices, v.43 n.6, June 2008
	Hyunchul Park , Kevin Fan , Manjunath Kudlur , Scott Mahlke, Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
	Praveen Raghavan , Andy Lambrechts , Murali Jayapala , Francky Catthoor , Diederik Verkest , Henk Corporaal, Very wide register: an asymmetric register file organization for low power embedded processors, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Surin Kittitornkun , Yu Hen Hu, Efficient implementation of nested-loop multimedia algorithms, EURASIP Journal on Applied Signal Processing, v.2001 n.1, p.129-146, 1 January 2001
	Michael Bedford Taylor , Walter Lee , Jason Miller , David Wentzlaff , Ian Bratt , Ben Greenwald , Henry Hoffmann , Paul Johnson , Jason Kim , James Psota , Arvind Saraf , Nathan Shnidman , Volker Strumpen , Matt Frank , Saman Amarasinghe , Anant Agarwal, Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams, ACM SIGARCH Computer Architecture News, v.32 n.2, p.2, March 2004
	Michael L. Chu , Scott A. Mahlke, Compiler-directed Data Partitioning for Multicluster Processors, Proceedings of the International Symposium on Code Generation and Optimization, p.208-220, March 26-29, 2006
	Satish Pillai , Margarida F. Jacome, Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling, Proceedings of the conference on Design, Automation and Test in Europe, p.10422, March 03-07, 2003
	Kevin Fan , Hyun hul Park , Manjunath Kudlur , S ott Mahlke, Modulo scheduling for highly customized datapaths to increase hardware reusability, Proceedings of the sixth annual IEEE/ACM international symposium on Code generation and optimization, April 05-09, 2008, Boston, MA, USA
	Enric Gibert , Jesús Sánchez , Antonio González, Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.315, December 03-05, 2003
	Hyunchul Park , Kevin Fan , Scott A. Mahlke , Taewook Oh , Heeseok Kim , Hong-seok Kim, Edge-centric modulo scheduling for coarse-grained reconfigurable architectures, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, October 25-29, 2008, Toronto, Ontario, Canada
	Yingchao Zhao , Chun Jason Xue , Minming Li , Bessie Hu, Energy-aware register file re-partitioning for clustered VLIW architectures, Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, January 19-22, 2009, Yokohama, Japan