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An integrated approach to accelerate data and predicate computations in hyperblocks
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Source International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents
Monterey, California, United States
Pages: 101 - 111  
Year of Publication: 2000
ISBN:1-58113-196-8
Authors
Alexandre E. Eichenberger  North Carolina State University, Raleigh, NC
Waleed Meleis  Northeastern University, Boston, MA
Suman Maradani  Northeastern University, Boston, MA
Sponsors
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Aug99
 
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Fis81
J. Fisher, Trace scheduling: a technique for global microcode compaction, IEEE Trans. on Comp, C-30:478-490, 1981.
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KSR94
V. Kathail, M. Schlansker, B. R. Rau, HPL PlayDoh Architecture Specification: Version 1.1, Computer Systems Laboratory, Hewlett Packard Technical Report HPL-93-80(R.1), 2000.
Ma92
 
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Rau98
B. R. Rau, V. Kathail, S. Aditya, Machine Description Driven Compilers for EPIC Processors, Technical Report HPL-98-40, Hewlett-Packard Laboratories, 1998.
SMJ99
 
Tri99
The Trimaran System, www.trimaran.org, 1999.


Collaborative Colleagues:
Alexandre E. Eichenberger: colleagues
Waleed Meleis: colleagues
Suman Maradani: colleagues