Efficient checker processor design

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Efficient checker processor design

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 87 - 97

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Saugata Chatterjee	Electrical Engineering and Computer Science Department, University of Michigan
Chris Weaver	Electrical Engineering and Computer Science Department, University of Michigan
Todd Austin	Electrical Engineering and Computer Science Department, University of Michigan

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 32, Citation Count: 9

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Todd M. Austin, DIVA: a reliable substrate for deep submicron microarchitecture design, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.196-207, November 16-18, 1999, Haifa, Israel
	2	T. Austin, DIVA: A Dynamic Approach to Microprocessor Verification, The Journal of Instruction-Level Parallelism Volume 2, 2000.
	3	Jean-Loup Baer , Tien-Fu Chen, An effective on-chip preloading scheme to reduce data access penalty, Proceedings of the 1991 ACM/IEEE conference on Supercomputing, p.176-186, November 18-22, 1991, Albuquerque, New Mexico, United States [doi>10.1145/125826.125932]
	4	M. Blum and H. Wasserman, Reflections on the Pentium Division Bug, Intel Corporation, Oct. 1997.
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	6	James Dundas , Trevor Mudge, Improving data cache performance by pre-executing instructions under a cache miss, Proceedings of the 11th international conference on Supercomputing, p.68-75, July 07-11, 1997, Vienna, Austria [doi>10.1145/263580.263597]
	7	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
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	10	Steven K. Reinhardt , Shubhendu S. Mukherjee, Transient fault detection via simultaneous multithreading, Proceedings of the 27th annual international symposium on Computer architecture, p.25-36, June 2000, Vancouver, British Columbia, Canada
	11	Eric Rotenberg, AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors, Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, p.84, June 15-18, 1999
	12	Timothy J. Slegel , Robert M. Averill III , Mark A. Check , Bruce C. Giamei , Barry W. Krumm , Christopher A. Krygowski , Wen H. Li , John S. Liptay , John D. MacDougall , Thomas J. McPherson , Jennifer A. Navarro , Eric M. Schwarz , Kevin Shum , Charles F. Webb, IBM's S/390 G5 Microprocessor Design, IEEE Micro, v.19 n.2, p.12-23, March 1999 [doi>10.1109/40.755464]
	13	Karthik Sundaramoorthy , Zach Purser , Eric Rotenburg, Slipstream processors: improving both performance and fault tolerance, Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, p.257-268, November 2000, Cambridge, Massachusetts, United States
	14	SPEC newsletter, Fairfax, Virginia, Sept. 1995.

CITED BY 9

	Maher Mneimneh , Fadi Aloul , Chris Weaver , Saugata Chatterjee , Karem Sakallah , Todd Austin, Scalable hybrid verification of complex microprocessors, Proceedings of the 38th conference on Design automation, p.41-46, June 2001, Las Vegas, Nevada, United States
	Youfeng Wu , Dong-Yuan Chen , Jesse Fang, Better exploration of region-level value locality with integrated computation reuse and value prediction, ACM SIGARCH Computer Architecture News, v.29 n.2, p.98-108, May 2001
	Toshinori Sato , Itsujiro Arita, Constructive timing violation for improving energy efficiency, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
	Milo M. K. Martin , Daniel J. Sorin , Harold W. Cain , Mark D. Hill , Mikko H. Lipasti, Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
	Todd Austin , Valeria Bertacco , David Blaauw , Trevor Mudge, Opportunities and challenges for better than worst-case design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Joonhyuk Yoo , Manoj Franklin, Hierarchical Verification for Increasing Performance in Reliable Processors, Journal of Electronic Testing: Theory and Applications, v.24 n.1-3, p.117-128, June 2008
	Jared C. Smolens , Jangwoo Kim , James C. Hoe , Babak Falsafi, Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.257-268, December 04-08, 2004, Portland, Oregon
	Jared C. Smolens , Brian T. Gold , Babak Falsafi , James C. Hoe, Reunion: Complexity-Effective Multicore Redundancy, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.223-234, December 09-13, 2006
	Demid Borodin , B. H. Juurlink , Said Hamdioui , Stamatis Vassiliadis, Instruction-Level Fault Tolerance Configurability, Journal of Signal Processing Systems, v.57 n.1, p.89-105, October 2009