A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality

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A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality

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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 32 - 41

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Zhao Zhang	Department of Computer Science, College of William and Mary, Williamsburg, VA
Zhichun Zhu
Xiaodong Zhang

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SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

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ACM New York, NY, USA

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Downloads (6 Weeks): 20, Downloads (12 Months): 112, Citation Count: 15

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REFERENCES

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	Hans Vandierendonck , Koen De Bosschere, XOR-Based Hash Functions, IEEE Transactions on Computers, v.54 n.7, p.800-812, July 2005
	Zhao Zhang , Zhichun Zhu , Xiaodong Zhang, Cached DRAM for ILP Processor Memory Access Latency Reduction, IEEE Micro, v.21 n.4, p.22-32, July 2001
	Design and Optimization of Large Size and Low Overhead Off-Chip Caches, IEEE Transactions on Computers, v.53 n.7, p.843-855, July 2004
	Mazen Kharbutli , Yan Solihin , Jaejin Lee, Eliminating Conflict Misses Using Prime Number-Based Cache Indexing, IEEE Transactions on Computers, v.54 n.5, p.573-586, May 2005
	Thomas Moscibroda , Onur Mutlu, Memory performance attacks: denial of memory service in multi-core systems, Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium, p.1-18, August 06-10, 2007, Boston, MA
	Daniel Gracia Perez , Gilles Mouchard , Olivier Temam, MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.43-54, December 04-08, 2004, Portland, Oregon
	Scott Rixner, Memory Controller Optimizations for Web Servers, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.355-366, December 04-08, 2004, Portland, Oregon
	Jun Shao , Brian T. Davis, The bit-reversal SDRAM address mapping, Proceedings of the 2005 workshop on Software and compilers for embedded systems, p.62-71, September 29-October 01, 2005, Dallas, Texas
	Abhas Kumar , Nisheet Jain , Mainak Chaudhuri, Long-latency branches: how much do they matter?, ACM SIGARCH Computer Architecture News, v.34 n.3, p.9-15, June 2006
	Engin Ipek , Onur Mutlu , José F. Martínez , Rich Caruana, Self-Optimizing Memory Controllers: A Reinforcement Learning Approach, ACM SIGARCH Computer Architecture News, v.36 n.3, p.39-50, June 2008
	Onur Mutlu , Thomas Moscibroda, Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, ACM SIGARCH Computer Architecture News, v.36 n.3, p.63-74, June 2008
	Hongzhong Zheng , Jiang Lin , Zhao Zhang , Eugene Gorbatov , Howard David , Zhichun Zhu, Mini-rank: Adaptive DRAM architecture for improving memory power efficiency, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.210-221, November 08-12, 2008
	Luke Yen , Stark C. Draper , Mark D. Hill, Notary: Hardware techniques to enhance signatures, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.234-245, November 08-12, 2008
	Hongzhong Zheng , Jiang Lin , Zhao Zhang , Zhichun Zhu, Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009
	Mainak Chaudhuri, Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, December 12-16, 2009, New York, New York