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International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 22 - 31

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Kevin M. Lepak	Electrical and Computer Engineering, University of Wisconsin, 1415 Engineering Drive, Madison, WI
Mikko H. Lipasti	Electrical and Computer Engineering, University of Wisconsin, 1415 Engineering Drive, Madison, WI

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 30, Citation Count: 14

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Gordon B. Bell , Kevin M. Lepak , Mikko H. Lipasti, Characterization of Silent Stores, Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques, p.133, October 15-19, 2000
	2	R. E. Blahut. Theory and Practice of Error Control Codes. Addison-Wesley Publishing Company, Reading, MA, 1983.
	3	J. Borkenhagen. Personal Communication. IBM Server Development. Rochester, MN, June 2000.
	4	J. Borkenhagen and S. Storino. 5th Generation 64-bit PowerPC- Compatible Commercial Processor Design. IBM Whitepaper, http://www.rs6000.ibm.com, 1999.
	5	D. C. Burger and T. M. Austin. The Simplescalar Tool Set, Version 2.0. Technical Report CS-TR-97-1342, University of Wisconsin, Madison, June 1997.
	6	Brad Calder , Glenn Reinman , Dean M. Tullsen, Selective value prediction, Proceedings of the 26th annual international symposium on Computer architecture, p.64-74, May 01-04, 1999, Atlanta, Georgia, United States
	7	Brad Calder , Peter Feller , Alan Eustace, Value profiling, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.259-269, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	8	R. P. Colwell and R. Steck. A 0.6um BiCMOS Processor with Dynamic Execution. In Proceedings of ISSCC. 1995.
	9	Compaq Computer Corp. Alpha 21264 Hardware Reference Manual DS-0027A-TE. http://www1.support.compaq.com/ alpha-tools/documentation/current/chip-docs.html. February, 2000.
	10	Jose Gonzalez , Antonio Gonzalez, Control-Flow Speculation through Value Prediction for Superscalar Processors, Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, p.57, October 12-16, 1999
	11	IBM Corporation. Fault Tolerance Decision in DRAM Applications. Application Note, http://www.chips.ibm.com/ products/memory/fault/fault.html. July, 1997.
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	14	Kevin M. Lepak , Mikko H. Lipasti, On the value locality of store instructions, Proceedings of the 27th annual international symposium on Computer architecture, p.182-191, June 2000, Vancouver, British Columbia, Canada
	15	Mikko H. Lipasti , John Paul Shen, Exceeding the dataflow limit via value prediction, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.226-237, December 02-04, 1996, Paris, France
	16	T. May and M. Woods. Alpha-particle-induced Soft Errors in Dynamic Memories. IEEE Transactions on Electronic Devices, 26(2), 1979.
	17	A. Mendelson and F. Gabbay. Speculative Execution Based on Value Prediction. Technical report, Technion, 1997. (http:// www-ee.technion.ac.il/.
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	19	Andreas Ioannis Moshovos , Gurindar S. Sohi, Memory dependence prediction, 1998
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	21	Eric Rotenberg, AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors, Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, p.84, June 15-18, 1999
	22	Paul I. Rubinfeld, Managing Problems at High Speed, Computer, v.31 n.1, p.47-48, January 1998
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	24	J. F. Ziegler, Terrestrial cosmic rays, IBM Journal of Research and Development, v.40 n.1, p.19-39, Jan. 1996
	25	J. F. Ziegler , H. W. Curtis , H. P. Muhlfeld , C. J. Montrose , B. Chin, IBM experiments in soft fails in computer electronics (1978–1994), IBM Journal of Research and Development, v.40 n.1, p.3-18, Jan. 1996

CITED BY 14

	Ilhyun Kim , Mikko H. Lipasti, Implementing optimizations at decode time, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
	Kevin M. Lepak , Gordon B. Bell , Mikko H. Lipasti, Silent Stores and Store Value Locality, IEEE Transactions on Computers, v.50 n.11, p.1174-1190, November 2001
	Jaehyuk Huh , Jichuan Chang , Doug Burger , Gurindar S. Sohi, Coherence decoupling: making use of incoherence, ACM SIGARCH Computer Architecture News, v.32 n.5, December 2004
	Ajeet Shankar , S. Subramanya Sastry , Rastislav Bodík , James E. Smith, Runtime specialization with optimistic heap analysis, ACM SIGPLAN Notices, v.40 n.10, October 2005
	Kevin M. Lepak , Mikko H. Lipasti, Temporally silent stores, ACM SIGARCH Computer Architecture News, v.30 n.5, December 2002
	Braxton Thomason , Craig Chase, Partially ordered epochs for thread-level speculation, Proceedings of the 2nd conference on Computing frontiers, May 04-06, 2005, Ischia, Italy
	Scott Friedman , Praveen Krishnamurthy , Roger Chamberlain , Ron K. Cytron , Jason E. Fritts, Dusty caches for reference counting garbage collection, ACM SIGARCH Computer Architecture News, v.34 n.1, March 2006
	Hossein Asadi , Vilas Sridharan , Mehdi B. Tahoori , David Kaeli, Vulnerability analysis of L2 cache elements to single event upsets, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Samantika Subramaniam , Gabriel H. Loh, Fire-and-Forget: Load/Store Scheduling with No Store Queue at All, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.273-284, December 09-13, 2006
	Tong Li , Alvin R. Lebeck , Daniel J. Sorin, Spin Detection Hardware for Improved Management of Multithreaded Systems, IEEE Transactions on Parallel and Distributed Systems, v.17 n.6, p.508-521, June 2006
	Ali Mahjur , Mahmud Taghizadeh , Amir Hossein Jahangir, Lazy instruction scheduling: keeping performance, reducing power, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Mohit Tiwari , Banit Agrawal , Shashidhar Mysore , Jonathan Valamehr , Timothy Sherwood, A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.94-105, November 08-12, 2008
	Julien Dusser , Thomas Piquet , André Seznec, Zero-content augmented caches, Proceedings of the 23rd international conference on Supercomputing, June 08-12, 2009, Yorktown Heights, NY, USA
	Ping Zhou , Bo Zhao , Jun Yang , Youtao Zhang, A durable and energy efficient main memory using phase change memory technology, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009