Eager writeback - a technique for improving bandwidth utilization

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Eager writeback - a technique for improving bandwidth utilization

Full text

Publisher Site , Pdf

Pdf (1.12 MB),

Ps (14.94 MB)

Source

International Symposium on Microarchitecture archive
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture table of contents

Monterey, California, United States

Pages: 11 - 21

Year of Publication: 2000

ISBN:1-58113-196-8

Authors

Hsien-Hsin S. Lee	ACAL, EECS Department, University Of Michigan, Ann Arbor, MI
Gary S. Tyson	ACAL, EECS Department, University Of Michigan, Ann Arbor, MI
Matthew K. Farrens	Department of Computer Science, University of California, Davis, CA

Sponsors

SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE TC - MICRO : IEEE TC - MICRO

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 36, Citation Count: 13

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/360128.360132 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Doug, c. Burger and Todd M. Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report 1342, Computer Science Department, University of Wiscosin-Madiscon, 1997.
	2	Intel Corporation. Pentium Pro Family Developer's Manual, volume 3: Operating System Writer's Manual. Intel Literature Centers, 1995.
	3	Intel Corporation. IA-64 Architecture Software Developer's Manual, Volume 2: IA-64 System Architecture. Intel Literature Centers, 2000.
	4	Rambus Corporation. Direct Rambus Memory Controller {RMCdll} Data Sheet. http://www.rambus.com/docs/RMC.dl.0036.00.s.pelf, 1999.
	5	Standard Performance Evaluation Corporation. SPEC CPU95 Benchmarks. http://www.specbench.org/org/cpu95/,1995.
	6	John L. Hennessy , David A. Patterson, Computer architecture (2nd ed.): a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1996
	7	David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
	8	An-Chow Lai , Babak Falsafi, Selective, accurate, and timely self-invalidation using last-touch prediction, Proceedings of the 27th annual international symposium on Computer architecture, p.139-148, June 2000, Vancouver, British Columbia, Canada
	9	Simplescalar Tool set. X benchmark suite. http://www.cs.wisc.edu/ austin /simple/xbenchmarks.tar.gr, 1998.
	10	Kevin Skadron , Douglas W. Clark, Design Issues and Tradeoffs for Write Buffers, Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture, p.144, February 01-05, 1997
	11	G. S. Sohi , S. Vajapeyam, Instruction issue logic for high-performance, interruptable pipelined processors, Proceedings of the 14th annual international symposium on Computer architecture, p.27-34, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30354]
	12	Alan Watt, 3d Computer Graphics, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1993
	13	Paul Zagadi, Deep Buch, Emile Hsich, Daniel Melaku, Vladimir Pentkovski, and Hsien-Hsin Lee. Architecture of a 3D Software Stack for Peak Pentium III. Processor Performance. Intel Technology Journal, Q2 1999. http://developer.intel.com/technology/fitj/q2 1999/arcticles/ art_4.htm.

CITED BY 13

	Stefanos Kaxiras , Zhigang Hu , Margaret Martonosi, Cache decay: exploiting generational behavior to reduce cache leakage power, ACM SIGARCH Computer Architecture News, v.29 n.2, p.240-251, May 2001
	Kevin M. Lepak , Gordon B. Bell , Mikko H. Lipasti, Silent Stores and Store Value Locality, IEEE Transactions on Computers, v.50 n.11, p.1174-1190, November 2001
	Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi, Let caches decay: reducing leakage energy via exploitation of cache generational behavior, ACM Transactions on Computer Systems (TOCS), v.20 n.2, p.161-190, May 2002
	Design and Optimization of Large Size and Low Overhead Off-Chip Caches, IEEE Transactions on Computers, v.53 n.7, p.843-855, July 2004
	Karthik Sankaranarayanan , Kevin Skadron, Profile-based adaptation for cache decay, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.3, p.305-322, September 2004
	Huiyang Zhou , Mark C. Toburen , Eric Rotenberg , Thomas M. Conte, Adaptive mode control: A static-power-efficient cache design, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.3, p.347-372, August 2003
	Daniel Gracia Perez , Gilles Mouchard , Olivier Temam, MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.43-54, December 04-08, 2004, Portland, Oregon
	Scott Rixner, Memory Controller Optimizations for Web Servers, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.355-366, December 04-08, 2004, Portland, Oregon
	Soontae Kim, Area-efficient error protection for caches, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Ismail Kadayif , Mahmut Kandemir, Modeling and improving data cache reliability: 1, ACM SIGMETRICS Performance Evaluation Review, v.35 n.1, June 2007
	Love Kothari , Nicholas P. Carter, Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices, IEEE Transactions on Computers, v.56 n.2, p.161-173, February 2007
	Ravi K. Venkatesan , Ahmed S. Al-Zawawi , Krishnan Sivasubramanian , Eric Rotenberg, ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling, IEEE Transactions on Computers, v.56 n.2, p.147-160, February 2007
	Doe Hyun Yoon , Mattan Erez, Memory mapped ECC: low-cost error protection for last level caches, ACM SIGARCH Computer Architecture News, v.37 n.3, June 2009