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ABSTRACT
This paper describes the CRAY-1, discusses the evolution of its architecture, and gives an account of some of the problems that were overcome during its manufacture.
The CRAY-1 is the only computer to have been built to date that satisfies ERDA's Class VI requirement (a computer capable of processing from 20 to 60 million floating point operations per second) [1].
The CRAY-1's Fortran compiler (CFT) is designed to give the scientific user immediate access to the benefits of the CRAY-1's vector processing architecture. An optimizing compiler, CFT, “vectorizes” innermost DO loops. Compatible with the ANSI 1966 Fortran Standard and with many commonly supported Fortran extensions, CFT does not require any source program modifications or the use of additional nonstandard Fortran statements to achieve vectorization. Thus the user's investment of hundreds of man months of effort to develop Fortran programs for other contemporary computers is protected.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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1
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CRAY-1 Final Evaluation by T. W. Keller, LASL, LA- 6456-MS.
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2
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CRAY-1 Report, Auerbach Computer Technology Report, Auerbach Publisher's, 6560 North Park Drive, Pennsauken, N. J. 08109.
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3
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Preliminary Report on Results of Matrix Benchmarks on Vector Processors: Calahan, Joy, Orbits, System Engineering Laboratory, University of Michigan, Ann Arbor, Michigan 48109.
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4
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Computer Architecture Issues in Large-Scale Systems, 9th Asilomar Conference, Naval Postgraduate School, Monterey, California.
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5
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Computer World, August 1976.
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6
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The IBM 360/195 by Jesse O'Murphy and Robert M. Wade, Datamation, April 1970.
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7
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Work done by Paul Johnson, Cray Research.
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8
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Work done by Richard Hendrickson, Cray Research.
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9
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The section on CRAY-1 development problems is based on remarks made by Seymour Cray in a speech to prospective CRAY-1 users in 1975.z
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CITED BY 131
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Roger Espasa , Mateo Valero , James E. Smith, Out-of-order vector architectures, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.160-170, December 01-03, 1997, Research Triangle Park, North Carolina, United States
|
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|
|
|
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Eiichi Goto , Tetsuo Ida , Kei Hiraki , Masayuki Suzuki , Nobuyuki Inada, FLATS, a machine for numerical, symbolic and associative computing, Proceedings of the 6th annual symposium on Computer architecture, p.102-110, April 23-25, 1979
|
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|
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|
|
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|
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Jesus Corbal , Roger Espasa , Mateo Valero, MOM: a matrix SIMD instruction set architecture for multimedia applications, Proceedings of the 1999 ACM/IEEE conference on Supercomputing (CDROM), p.15-es, November 14-19, 1999, Portland, Oregon, United States
|
|
|
G. S. Sohi , S. Vajapeyam, Instruction issue logic for high-performance, interruptable pipelined processors, Proceedings of the 14th annual international symposium on Computer architecture, p.27-34, June 02-05, 1987, Pittsburgh, Pennsylvania, United States
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
William Y. Chen , Scott A. Mahlke , Wen-mei W. Hwu , Tokuzo Kiyohara , Pohua P. Chang, Tolerating data access latency with register preloading, Proceedings of the 6th international conference on Supercomputing, p.104-113, July 19-24, 1992, Washington, D. C., United States
|
|
|
Tokuzo Kiyohara , Scott Mahlke , William Chen , Roger Bringmann , Richard Hank , Sadun Anik , Wen-Mei Hwu, Register connection: a new approach to adding registers into instruction set architectures, ACM SIGARCH Computer Architecture News, v.21 n.2, p.247-256, May 1993
|
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|
|
|
|
Ujval J. Kapasi , William J. Dally , Scott Rixner , Peter R. Mattson , John D. Owens , Brucek Khailany, Efficient conditional operations for data-parallel architectures, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.159-170, December 2000, Monterey, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
Scott A. Mahlke , William Y. Chen , Roger A. Bringmann , Richard E. Hank , Wen-Mei W. Hwu , B. Ramakrishna Rau , Michael S. Schlansker, Sentinel scheduling: a model for compiler-controlled speculative execution, ACM Transactions on Computer Systems (TOCS), v.11 n.4, p.376-408, Nov. 1993
|
|
|
|
|
|
J. H. Tang , E. S. Davidson , J. Tong, Polycyclic Vector scheduling vs. Chaining on 1-Port Vector supercomputers, Proceedings of the 1988 ACM/IEEE conference on Supercomputing, p.122-122, November 12-17, 1988, Orlando, Florida, United States
|
|
|
Tsutomu Hoshino , Toshio Kawai , Tomonori Shirakawa , Junchi Higashino , Akira Yamaoka , Hachidai Ito , Takashi Sato , Kazuo Sawada, PACS: a parallel microprocessor array for scientific calculations, ACM Transactions on Computer Systems (TOCS), v.1 n.3, p.195-221, August 1983
|
|
|
|
|
|
|
|
|
K. Cheung , G. Sohi , K. Saluja , D. Pradhan, Organization and analysis of a gracefully-degrading interleaved memory system, Proceedings of the 14th annual international symposium on Computer architecture, p.224-231, June 02-05, 1987, Pittsburgh, Pennsylvania, United States
|
|
|
|
|
|
John D. Owens , William J. Dally , Ujval J. Kapasi , Scott Rixner , Peter Mattson , Ben Mowery, Polygon rendering on a stream architecture, Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware, p.23-32, August 21-22, 2000, Interlaken, Switzerland
|
|
|
|
|
|
|
|
|
Tetsuo Hironaka , Takashi Hashimoto , Keizo Okazaki , Kazuaki Murakami , Shinji Tomita, Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architecture, Proceedings of the 6th international conference on Supercomputing, p.272-281, July 19-24, 1992, Washington, D. C., United States
|
|
|
|
|
|
|
|
|
|
|
|
Yoji Yamada , John Gyllenhall , Grant Haab , Wen-mei Hwu, Data relocation and prefetching for programs with large data sets, Proceedings of the 27th annual international symposium on Microarchitecture, p.118-127, November 30-December 02, 1994, San Jose, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Makoto Hasegawa , Tadao Nakamura , Yoshiharu Shigei, Distributed communicating media-a multitrack bus-capable of concurrent data exchanging, Proceedings of the 8th annual symposium on Computer Architecture, p.367-372, May 12-14, 1981, Minneapolis, Minnesota, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
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|
|
|
|
|
|
|
Brucek Khailany , William J. Dally , Ujval J. Kapasi , Peter Mattson , Jinyung Namkoong , John D. Owens , Brian Towles , Andrew Chang , Scott Rixner, Imagine: Media Processing with Streams, IEEE Micro, v.21 n.2, p.35-46, March 2001
|
|
|
|
|
|
|
|
|
Ujval J. Kapasi , Scott Rixner , William J. Dally , Brucek Khailany , Jung Ho Ahn , Peter Mattson , John D. Owens, Programmable Stream Processors, Computer, v.36 n.8, p.54-62, August 2003
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
Ian Buck , Tim Foley , Daniel Horn , Jeremy Sugerman , Kayvon Fatahalian , Mike Houston , Pat Hanrahan, Brook for GPUs: stream computing on graphics hardware, ACM Transactions on Graphics (TOG), v.23 n.3, August 2004
|
|
|
|
|
|
|
|
|
Ronny Krashinsky , Christopher Batten , Mark Hampton , Steve Gerding , Brian Pharris , Jared Casper , Krste Asanovic, The Vector-Thread Architecture, IEEE Micro, v.24 n.6, p.84-90, November 2004
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
John Nickolls , L. J. Madar III , Scott Johnson , Viresh Rustagi , Ken Unger , Mustafiz Choudhury, Calisto: A Low-Power Single-Chip Multiprocessor Communications Platform, IEEE Micro, v.23 n.2, p.29-43, March 2003
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Christopher Batten , Ronny Krashinsky , Steve Gerding , Krste Asanovic, Cache Refill/Access Decoupling for Vector Machines, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.331-342, December 04-08, 2004, Portland, Oregon
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Mattan Erez , Jung Ho Ahn , Jayanth Gummaraju , Mendel Rosenblum , William J. Dally, Executing irregular scientific applications on stream architectures, Proceedings of the 21st annual international conference on Supercomputing, June 17-21, 2007, Seattle, Washington
|
|
|
Ronny Krashinsky , Christopher Batten , Mark Hampton , Steve Gerding , Brian Pharris , Jared Casper , Krste Asanovic, The Vector-Thread Architecture, ACM SIGARCH Computer Architecture News, v.32 n.2, p.52, March 2004
|
|
|
|
|
|
|
|
|
|
|
|
Aaron Smith , Ramadass Nagarajan , Karthikeyan Sankaralingam , Robert McDonald , Doug Burger , Stephen W. Keckler , Kathryn S. McKinley, Dataflow Predication, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.89-102, December 09-13, 2006
|
|
|
William J. Dally , Francois Labonte , Abhishek Das , Patrick Hanrahan , Jung-Ho Ahn , Jayanth Gummaraju , Mattan Erez , Nuwan Jayasena , Ian Buck , Timothy J. Knight , Ujval J. Kapasi, Merrimac: Supercomputing with Streams, Proceedings of the 2003 ACM/IEEE conference on Supercomputing, p.35, November 15-21, 2003
|
|
|
J. R. Goodman , Jian-tu Hsieh , Koujuch Liou , Andrew R. Pleszkun , P. B. Schechter , Honesty C. Young, PIPE: a VLSI decoupled architecture, ACM SIGARCH Computer Architecture News, v.13 n.3, p.20-27, June 1985
|
|
|
|
|
|
|
|
|
Silviu Ciricescu , Ray Essick , Brian Lucas , Phil May , Kent Moat , Jim Norris , Michael Schuette , Ali Saidi, The Reconfigurable Streaming Vector Processor (RSVPTM), Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.141, December 03-05, 2003
|
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|
|
|
|
|
|
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|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
|
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Eiichi Goto , Tetsuo Ida , Kei Hiraki , Masayuki Suzuki , Nobuyuki Inada, Flats, a machine for numerical, symbolic and associative computing, Proceedings of the 6th international joint conference on Artificial intelligence, p.1058-1066, August 20-23, 1979, Tokyo, Japan
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