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 REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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AMDAHL CORPORATION. Amdah1580 Technical Introduction. Amdahl Corporation, Sunnyvale, Calif. 1982.
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AMDAHL, G. The validity of the single processor approach to achieving large-scale computing capabilities, in Proceedings of AFIPS Spring Joint Computer Conference (Atlantic City, N.J., Apr. 18-20), AFIPS Press, Reston, Va., pp. 483-485.
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ANDERSON, D.W., SPARACIO, F.J., AND TOMASULO, R.M. The IBM System/360 Model 91: Machine philosophy and instruction handling. IBM J. Res. Devel. 11, 1 (Jan. 1967), 8-24.
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ARNOLD, C.N. Performance evaluation of three automatic vectorizer packages. In 1982 International Conference on Parallel Processing (Bellaire, Mich., Aug.) IEEE, New York 1982, pp. 235-242.
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BONSEIGNEUR, P. Description of the 7600 computer system. Comput. Group News 3, 5 (May 1969) 11-15.
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BRANTLEY, W.C., AND WIESS, J. Organization and architecture tradeoffs in FOM. In IEEE International Workshop on Computer Systems Organization, (New Orleans, La. Mar. 29-31), IEEE, New York, 1983, pp. 139-143.
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COHLER, E.U., AND STORER, J.E. Functionally parallel architecture for array processors. Computer 14, 9 (Sept. 1981), 28-36.
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CONNORS, W.D., FLORKOWSKI, J.H., AND PATTON, S.K. The IBM 3033: An inside look. Datamation 25, 5 (May 1979), 198-218.
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Co-Processor cooperates with 8 or 16-bit microprocessors. Electron. Des. 28, (Mar. 1980), p. 19.
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CRAY RESEARCH. CRAY X-MP Series Mainframe Reference Manual. Cray Research, Inc., Chippewa Falls, Wis. 1982.
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CRAY RESEARCH. CRA Y-1 Computer System Hardware Reference Manual. Cray Research, Inc., Chippewa Falls, Wis. 1976.
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FLYNN, M.J. Very high-speed computing systems. In Proceedings of the IEEE 54, 12 (Dec. 1966), 1901-1909.
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HINTZ, R.G., AND TATE, D.P. Control data STAR-100 processor design. In Proceedings of the IEEE Comcon 1972, IEEE, New York, (Sept.). 1972, pp. 1-4.
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KOZDROWICK{, E.W., AND THEIS, D.J. Second generation of vector supercomputers. Computer 13, 11 (Nov. 1980), 71-83.
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LINCOLN, N.R. Technology and design tradeoffs in the creation of a modern supercomputer. IEEE Trans. Comp. C-31, 5 (May 1982), 349-362.
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MCMAHON, F.H. FORTRAN CPU performance analysis. Lawrence Livermore Laboratories, Livermore, Calif., 1972.
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PANG, N.R., AND SMITH, J.E. CRAY-1 simulation tools. Tech. Rep. Electrical and Computer Engineering Dept., Univ. of Wisconsin, Madison, Wis. Dec. 1983.
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PLESZKUN, A.R., AND DAVIDSON, E.S. A structural memory access architecture. In 1983 International Conference on Parallel Processing (Bellaire Mich., Aug. 23-26) IEEE, New York, 1983.
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SMITH, J.E., AND KAMINSKI, T.J. Varieties of decoupled access/execute architectures. In Proceedings o{ the 20th Allerton Conference (Oct.). Univ. of Illinois, Monticello, Ill. 1982, pp. 577-586.
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SMITH, J.E., PLESZKUN, A.R., KATZ, R.H., AND GOODMAN, J.R. PIPE: A high performance VLSI architecture, in IEEE International Workshop on Computer Systems Organization (Mar.). IEEE, New York, 1983, pp. 131-138.
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WORLTON, J. Supercomputers: The philosophy behind the machines. Computerworld IN DEPTH Sect. (Nov. 9, 1981), In depth 1-14
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CITED BY 32
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William Mangione-Smith , Santosh G. Abraham , Edward S. Davidson, Register requirements of pipelined processors, Proceedings of the 6th international conference on Supercomputing, p.260-271, July 19-24, 1992, Washington, D. C., United States
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J. R. Goodman , Jian-tu Hsieh , Koujuch Liou , Andrew R. Pleszkun , P. B. Schechter , Honesty C. Young, PIPE: a VLSI decoupled architecture, ACM SIGARCH Computer Architecture News, v.13 n.3, p.20-27, June 1985
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Alastair D. Reid , Krisztian Flautner , Edmund Grimley-Evans , Yuan Lin, SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
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Chris Zimmer , Stephen Roderick Hines , Prasad Kulkarni , Gary Tyson , David Whalley, Facilitating compiler optimizations through the dynamic mapping of alternate register structures, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
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