Decoupled access/execute computer architectures

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Decoupled access/execute computer architectures

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ACM Transactions on Computer Systems (TOCS) archive
Volume 2 , Issue 4 (November 1984) table of contents

Pages: 289 - 308

Year of Publication: 1984

ISSN:0734-2071

Author

James E. Smith

Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 5, Downloads (12 Months): 95, Citation Count: 32

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	William Mangione-Smith , Santosh G. Abraham , Edward S. Davidson, Register requirements of pipelined processors, Proceedings of the 6th international conference on Supercomputing, p.260-271, July 19-24, 1992, Washington, D. C., United States
	Alan Jay Smith , Rafael H. Saavedra, Measuring Cache and TLB Performance and Their Effect on Benchmark Runtimes, IEEE Transactions on Computers, v.44 n.10, p.1223-1235, October 1995
	Joan-Manuel Parcerisa , Antonio Gonzalez, Improving Latency Tolerance of Multithreading through Decoupling, IEEE Transactions on Computers, v.50 n.10, p.1084-1094, October 2001
	Peter L. Bird , Alasdair Rawsthorne , Nigel P. Topham, The effectiveness of decoupling, Proceedings of the 7th international conference on Supercomputing, p.47-56, July 19-23, 1993, Tokyo, Japan
	Manuel E. Benitez , Jack W. Davidson, Code generation for streaming: an access/execute mechanism, ACM SIGPLAN Notices, v.26 n.4, p.132-141, Apr. 1991
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	Shlomo Weiss , James E. Smith, A study of scalar compilation techniques for pipelined supercomputers, ACM Transactions on Mathematical Software (TOMS), v.16 n.3, p.223-245, Sept. 1990
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	L. Kurian , P. T. Hulina , L. D. Coraor, Memory Latency Effects in Decoupled Architectures, IEEE Transactions on Computers, v.43 n.10, p.1129-1139, October 1994
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	William Mangione-Smith , Santosh G. Abraham , Edward S. Davidson, A Performance Comparison of the IBM RS/6000 and the Astronautics ZS-1, Computer, v.24 n.1, p.39-46, January 1991
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	Chunyue Liu , Xing Qin , Xiaolang Yan, Explicit data organization SIMD instruction set architecture for media processors, Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: parallel and distributed computing and networks, p.227-232, February 13-15, 2007, Innsbruck, Austria
	Mostafa I. Soliman , Samir A. Mohamed, A highly efficient implementation of back propagation algorithm using matrix instruction set architecture, Neural, Parallel & Scientific Computations, v.15 n.1, p.1-26, March 2007
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