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Architecture and design of AlphaServer GS320
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Source ACM SIGPLAN Notices archive
Volume 35 ,  Issue 11  (November 2000) table of contents
Pages: 13 - 24  
Year of Publication: 2000
ISSN:0362-1340
Authors
Kourosh Gharachorloo  Western Research Laboratory, Compaq Computer Corporation, Palo Alto, California
Madhu Sharma  High Performance Servers Division, Compaq Computer Corporation, Marlborough, Massachusetts
Simon Steely  High Performance Servers Division, Compaq Computer Corporation, Marlborough, Massachusetts
Stephen Van Doren  High Performance Servers Division, Compaq Computer Corporation, Marlborough, Massachusetts
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer GS320 architecture is specifically targeted at medium-scale multiprocessing with 32 to 64 processors. Each node in the design consists of four Alpha 21264 processors, up to 32GB of coherent memory, and an aggressive IO subsystem. The current implementation supports up to 8 such nodes for a total of 32 processors. While snoopy-based designs have been stretched to medium-scale multiprocessors by some vendors, providing sufficient snoop bandwidth remains a major challenge especially in systems with aggressive processors. At the same time, directory protocols targeted at larger scale designs lead to a number of inherent inefficiencies relative to snoopy designs. A key goal of the AlphaServer GS320 architecture has been to achieve the best-of-both-worlds, partly by exploiting the bounded scale of the target systems.This paper focuses on the unique design features used in the AlphaServer GS320 to efficiently implement coherence and consistency. The guiding principle for our directory-based protocol is to address correctness issues related to rare protocol races without burdening the common transaction flows. Our protocol exhibits lower occupancy and lower message counts compared to previous designs, and provides more efficient handling of 3-hop transactions. Furthermore, our design naturally lends itself to elegant solutions for deadlock, livelock, starvation, and fairness. The AlphaServer GS320 architecture also incorporates a couple of innovative techniques that extend previous approaches for efficiently implementing memory consistency models. These techniques allow us to generate commit events (which are used for ordering purposes) well in advance of formulating the reply to a transaction. Furthermore, the separation of the commit event allows time-critical replies to bypass inbound requests without violating ordering properties. Even though our design specifically targets medium-scale servers, many of the same techniques can be applied to larger-scale directory-based and smaller-scale snoopy-based designs. Finally, we evaluate the performance impact of some of the above optimizations and present a few competitive benchmark results.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Collaborative Colleagues:
Kourosh Gharachorloo: colleagues
Madhu Sharma: colleagues
Simon Steely: colleagues
Stephen Van Doren: colleagues